20
Rev NR
The Almost Flag value represents the number of bytes from each respective “end” of the FIFO. The Almost Empty
value represents the number of bytes from empty, and the Almost Full value represents the number of bytes from full
(NOT the number of bytes from empty). For example, the default value of “0x0007 0007” in the FIFO Almost
Register means that the Almost Empty Flag will indicate when the FIFO holds 7 bytes or fewer. It will transition as
the 8
th
byte is read or written. In this example, the Almost Full Flag will indicate that the FIFO contains (FIFO Size
– 7) bytes or more. For the standard 32Kbyte FIFO, an Almost Full value of 7 will cause the Almost Full flag to be
asserted when the FIFO contains 32761 (32k – 7) or more bytes of data .
The values placed in the FIFO Almost Registers take effect immediately, but should be set while the FIFO is empty
(or the FIFO should be reset following the change). Note that this is a little different than the method for FIFO Flag
programming which has previously been implemented on SIO4 boards. No FIFO programming delay is necessary.
3.2.2
FIFO Counters
The FIFO Size and FIFO count registers can be used to determine the exact amount of data in a FIFO as well as the
amount of free space remaining in a FIFO. The size of each FIFO is auto-detected following a board reset. Real-
time FIFO counters report the exact number of data words currently in each FIFO. By utilizing this information, the
user can determine the exact amount of data which can safely be transferred to the transmit FIFOs or transferred
from the receive FIFO. This information should help streamline data transfers by eliminating the need to
continuously check empty and full flags, yet still allow larger data blocks to be transferred.
3.2.3
FIFO Size
Unlike previous SIO4 boards which had ordering options for different FIFO sizes, the PCIe-SIO4BX2 always uses
32k byte deep FIFOs.
3.3
Board vs. Channel Registers
Since four serial channels are implemented on a single board, some registers apply to the entire board, while others
are unique to each channel. It is intended that each channel can act independently, but the user must keep in mind
that certain accesses will affect the entire board. Typically, the driver will adequately handle keeping board and
channel interfaces separate. However, the user must also be mindful that direct access to certain registers will affect
the entire board, not just a specific channel.
The Board Control and Board Status registers provide board level controls. Fundamentally, a board reset will do
just that, reset all the GSC registers and FIFOs to their default state. Interrupt control is also shared among all
registers, although local bits are segregated by channel. The device driver should take care of appropriately handling
the inter-mixed channel interrupts and pass them on to the application appropriately.
