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CHAPTER 3: PROGRAMMING
3.0
Introduction
This section addresses common programming questions when developing an application for the SIO8BX2. General
Standards has developed software libraries to simplify application development. These libraries handle many of the
low-level issues described below, including Resets, FIFO programming, and DMA. These libraries may default the
board to a “standard” configuration (one used by most applications), but still provide low-level access so
applications may be customized. The following sections describe the hardware setup in detail for common
programming issues.
3.1
Resets
Each serial channel provides control for four unique reset sources: a USC Reset, a Channel Reset, a Transmit FIFO
Reset, and a Receive FIFO Reset. All resets are controlled from the GSC Channel Control/Status Registers. In
addition, a Board Reset has been implemented in the Board Control Register. This board reset will reset all local
registers to their default state as well as reset all FIFOs and USCs (all channels will be reset).
It is important to realize that since each Zilog Z16C30 chip contains two serial channels, a USC Reset to either
channel will reset the entire chip (both channels affected). Due to the limitation of a USC Reset to affecting two
channels, it is recommended that a single USC Channel be Reset via the RTReset bit of the USC Channel
Command/Address Register (CCAR), as well as the Channel Reset.
The FIFO resets allow each individual FIFO (Tx and Rx) to be reset independently. Setting the FIFO reset bit will
clear the FIFO immediately.
3.2
FIFOs
Deep transmit and receive FIFOs are the key to providing four high speed serial channels without losing data.
Several features have been implemented to help in managing the on-board FIFOs. These include FIFO flags (Empty,
Full, Almost Empty and Almost Full) presented as both real-time status bits and interrupt sources, and individual
FIFO counters to determine the exact FIFO fill level. DMA of data to/from the FIFOs provides for fast and efficient
data transfers.
A single memory address is used to access both transmit and receive FIFOs for each channel. Data written to this
memory location will be written to the transmit FIFO, and data read from this location retrieves data from the receive
FIFO. Individual resets for the FIFOs are also provided in the Channel Control/Status Register.
3.2.1
FIFO Flags
Four FIFO flags are present from each on-board FIFO: FIFO Empty, FIFO Full, FIFO Almost Empty, and FIFO
Almost Full. These flags may be checked at any time from the Channel Control/Status Register. Note these flags are
presented as active low signals (‘0’ signifies condition is true). The Empty and Full flags are asserted when the FIFO
is empty or full, respectively. The Almost Empty and Almost Full flags are software programmable such that they
may be asserted at any desired fill level. This may be useful in determining when a data transfer is complete or to
provide an indicator that the FIFO is in danger of overflowing and needs immediate service.
