17
Rev NR
Since the USC Reset physically resets the USC, the first access to the USC following the reset must reinitialize the
BCR in the USC. To complete the Reset process, the user should write data 0x00 to USC base address offset 0x100
or 0x300 to correctly initialize the BCR. Following this initial byte write, the USC may be accessed normally.
Due to the ability for a USC Reset to affect two channels, it is recommended that a single USC Channel be Reset via
the RTReset bit of the USC Channel Command/Address Register (CACR).
2.2.2 8-Bit USC Register Access
As the USC has a configurable bus interface, the USC must be set to match the 8-bit non-multiplex interface
implementation of the SIO8BX2. This setup information must be programmed into the USC Bus Configuration
Register (BCR) upon initial power up and following every hardware reset of the USC. The BCR is accessible only
following a USC hardware reset – the first write to the USC following a USC Reset programs the BCR. Even though
the Zilog manual states the BCR has no specific address, the driver must use the channel USC base address – 0x100
for Ch 1 & Ch 2, 0x300 for Ch 3 & Ch 4 – as the BCR address. Failure to do so may result in improper setup. Since
the user interface to the USC is an 8 bit interface, the software only needs to set the lower byte to 0x00 (hardware
implementation will program the upper byte of the BCR).
2.2.3 USC Data Transfer
Although the Z16C30 USC contains 32 byte internal FIFOs for data transfer, these are typically not used on the
SIO8BX2. Since the SIO8BX2 has much deeper external FIFOs (or internal FPGA FIFOs), the internal USC FIFOs
are setup to immediately transfer data to/from the external FIFOs. Immediate transfer of received data to the
external FIFOs eliminates the possibility of data becoming “stuck” in the USC internal receive FIFOs, while
bypassing the USC internal transmit FIFOs ensures better control of the transmit data.
In order to automatically transfer data to and from the external FIFOs, the USC should use DMA to request a data
transfer whenever one byte is available in the USC internal FIFOs. This “DMA” should not be confused with the
DMA of data from the SIO8BX2 external FIFOs to the PCI interface. To accomplish the USC-to-External FIFO
DMA transfer, the TxReq/RxReq pins should be set as DMA Requests in the IOCR, and the TxAck/RxAck pins
should be set as DMA Acknowledge inputs in the HCR. In addition, the Tx Request Level should be set to 0x1F
(31) using TCSR/TICR and the Rx Request Level should be set to 0 using RCSR/RICR. See Z16C30 manual for
further details on programming the DMA request levels.
