10
Rev NR
IRQ14
Channel
4 Rx FIFO Almost Full
Rising Edge
Falling Edge
IRQ15
Channel
4 USC Interrupt
Level Hi
NONE
IRQ16
Channel
1 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ17
Channel
1 Tx FIFO Full
Rising Edge
Falling Edge
IRQ18
Channel
1 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ19
Channel
1 Rx FIFO Full
Rising Edge
Falling Edge
IRQ20
Channel
2 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ21
Channel
2 Tx FIFO Full
Rising Edge
Falling Edge
IRQ22
Channel
2 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ23
Channel
2 Rx FIFO Full
Rising Edge
Falling Edge
IRQ24
Channel
3 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ25
Channel
3 Tx FIFO Full
Rising Edge
Falling Edge
IRQ26
Channel
3 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ27
Channel
3 Rx FIFO Full
Rising Edge
Falling Edge
IRQ28
Channel
4 Tx FIFO Empty
Rising Edge
Falling Edge
IRQ29
Channel
4 Tx FIFO Full
Rising Edge
Falling Edge
IRQ30
Channel
4 Rx FIFO Empty
Rising Edge
Falling Edge
IRQ31
Channel
4 Rx FIFO Full
Rising Edge
Falling Edge
For all interrupt registers, the IRQ source (IRQ31:IRQ0) will correspond to the respective data bit (D31:D0) of each
register. (D0 = IRQ0, D1 = IRQ1, etc.)
All FIFO interrupts are edge triggered active high. This means that an interrupt will be asserted (assuming it is
enabled) when a FIFO Flag transitions from FALSE to TRUE (rising edge triggered) or TRUE to FALSE (falling
edge). For example: If Tx FIFO Empty Interrupt is set for Rising Edge Triggered, the interrupt will occur when the
FIFO transitions from NOT EMPTY to EMPTY. Likewise, if Tx FIFO Empty Interrupt is set as Falling Edge
Triggered, the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY.
All Interrupt Sources share a single interrupt request back to the PCI9056 PLX chip. Likewise, all USC interrupt
sources share a single interrupt request back to the interrupt controller and must be further qualified in the USC.
2.1.10.1
Interrupt Control: Local Offset 0x0060
The Interrupt Control register individually enables each interrupt source. A ‘1’ enables each interrupt source; a ‘0’
disables. An interrupt source must be enabled for an interrupt to be generated.
2.1.10.2
Interrupt Status/Clear: Local Offset 0x0064
The Interrupt Status Register shows the status of each respective interrupt source. If an interrupt source is enabled in
the Interrupt Control Register, a ‘1’ in the Interrupt Status Register indicates the respective interrupt has occurred.
The interrupt source will remain latched until the interrupt is cleared, either by writing to the Interrupt Status/Clear
Register with a ‘1’ in the respective interrupt bit position, or the interrupt is disabled in the Interrupt Control register.
If an interrupt source is not asserted or the interrupt is not enabled, writing a ‘1’ to that bit in the Interrupt
Status/Clear Register will have no effect on the interrupt.
If the interrupt source is a level triggered interrupt (USC interrupt), the interrupt status may still be ‘1’ even if the
interrupt is disabled. This indicates the interrupt condition is true, regardless of whether the interrupt is enabled.
