8
Rev NR
2.1.6
Channel RX Almost Flags: Local Offset 0x0014 / 0x0024 / 0x0034 / 0x0044
The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs. The
Almost Full/Empty Flags may be read as status bits in the Channel Control/Status Register, and are also edge-
triggered interrupt sources to the Interrupt Register.
D31:16
RX Almost Full Flag Value
Number of words from FIFO Full when the Almost Full Flag will be asserted (i.e.
FIFO contains {FIFO Size – Almost Full Value} words or more.)
D15:0
RX Almost Empty Flag Value
Number of words from FIFO Empty when the Almost Empty Flag will be asserted
2.1.7
Channel FIFO: Local Offset 0x0018 / 0x0028 / 0x0038 / 0x0048
The Channel FIFO Register passes serial data to/from the serial controller. The same register is used to access both
the Transmit FIFO (writes) and Receive FIFO (reads).
D31:8
RESERVED
D7:0
Channel FIFO Data
2.1.8
Channel Control/Status: Local Offset 0x001C / 0x002C / 0x003C / 0x004C
The Channel Control/Status Register provides the reset functions and data transceiver enable controls, and the FIFO
Flag status for each channel.
D31:24
RESERVED
D23:20
LED Control
Each Channel controls 2 LEDs on the back of the PCB. See Section 5.3 for more detailed
information about the LEDs.
D19
RESERVED
D18:8 Channel Status Bits
D18
Rx FIFO Underflow
D17
Tx FIFO Overflow (Latched)
D16
Rx FIFO Overflow (Latched)
1= Rx Data was lost due to Rx Overflow.
Note:
This bit is latched. Write D16=1 to clear.
D15
Rx FIFO Full Flag Lo
(0 = Rx FIFO Full)
D14
Rx FIFO Almost Full Flag Lo
(0 = Rx FIFO Almost Full)
D13
Rx FIFO Almost Empty Flag Lo
(0 = Rx FIFO Almost Empty)
D12
Rx FIFO Empty Flag Lo
(0 = Rx FIFO Empty)
D11
Tx FIFO Full Flag Lo
(0 = Tx FIFO Full)
D10
Tx FIFO Almost Full Flag Lo
(0 = Tx FIFO Almost Full)
D9
Tx FIFO Almost Empty Flag Lo
(0 = Tx FIFO Almost Empty)
D8
Tx FIFO Empty Flag Lo
(0 = Tx FIFO Empty)
