Getting Started with Cinterion
®
PLS62-W
4 Appendix: Circuit Diagrams for Evaluation Module Board
16
PLS62-W_startup_guide_v01
2018-05-17
Confidential / Released
Page 15 of 17
4
Appendix: Circuit Diagrams for Evaluation Module Board
Figure 8:
Schematic sheet 1
TP_ANT_DRX
TP_DRX_GND1
TP_DRX_GND2
GND
DIV_RX_ANT_IN_1
X107
2
3
1
0R
R101
GND
GND
22n
L100
ANT_GPS
SDIO_CMD
RF_OUT
VGPS
TP_ANT_GPS
X105
2
3
1
TP_GPS_GND2
MICN1
X106
2
3
1
TP_GPS_GND1
0R
R100
0R
R102
2p2
C103
0R
R103
2p2
C105
GND
GND
GND
EPP1
F r q C t r l
AGND
GND
SDIO1
CMIM_VCC
GND
G16
G15
G14
G13
G4
G3
G2
G1
F16
F15
F14
F13
F4
F3
F2
F1
E16
E15
E14
E13
E12
E5
E4
E3
E2
E1
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
H1
H2
H3
H4
H13
H14
H15
H16
J 1
J 2
J 3
J 4
J 1 3
J 1 4
J 1 5
J 1 6
K1
K2
K3
K4
K5
K12
K13
K14
K15
K16
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
ALS3_Copper
XG100
G16
G15
G14
G13
G4
G3
G2
G1
F16
F15
F14
F13
F4
F3
F2
F1
E16
E15
E14
E13
E12
E5
E4
E3
E2
E1
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
H1
H2
H3
H4
H13
H14
H15
H16
J 1
J 2
J 3
J 4
J 1 3
J 1 4
J 1 5
J 1 6
K1
K2
K3
K4
K5
K12
K13
K14
K15
K16
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
TP_ANT_WGSM
ANT_GPS
1 p
C100
TP_WGSM_GND2
TP_WGSM_GND1
GND
TX_Act
0R
R104
GND
GND
GND
GND
EPN1
VMIC
22n
L101
MICP1
ANT_GPS_DC
PWM1/SDIO2/GPIO7
I2CDAT
CC2IO_I
GPIO11
CC2RST_I
COUNTER/SDIO3/GPIO8
CC2IN
DIV_RX_ANT_IN_1
I2CCLK
STATUS/SDIO_CLK/GPIO5
GPIO25
CC2CLK_I
RXD0
GPIO14
TXDDAI/GPIO20
SIM_SW/GPIO26
DSR0/SPI_CLK/GPIO3
EMERG_OFF
VMMC
VUSB
RF_OUT
TFSDAI/GPIO22
GPIO13
RING0/GPIO24
GPIO6/PWM2
CCCLK_I
RXD1/SPI_MOSI/GPIO16
USB_DP
IGT
RXDDAI/GPIO21
GPIO15
CTS0
V S I M _ I
CCIO_I
TXD1/SPI_MISO/GPIO17
USB_DN
CCRST_I
ADC1
RTS0
V180
PWR_IND
FAB_TP1
RTS1/GPIO18
GPIO4/FAST_SHDN
GPIO12
BATT_PWR
CCIN
DTR0/SDIO_CD/GPIO1
TXD0
SCLK/GPIO23
EMERG_RST
DCD0/SDIO0/GPIO2
V S I M 2 _ I
CTS1/SPI_CS/GPIO19
VRTC
0 R
R111
CC2CLK
CC2IO_I
CC2IO
220n
C107
SIMSEL
0 R
R115
4 k 7
R112
CC2RST
CC2RST_I
CC2CLK
GND
CCRST_I
0 R
R114
CCCLK
VSIM2
GND
VSIM_I
CCIO_I
0 R
R113
CCRST
CC2IO
GND
GND
2DAT
VCC
NC
SEL
VSIM
RST
CLK
DAT
HEATPAD
1DAT
2CLK
1CLK
1RST
2RST
2VSIM
1VSIM
F S A 2 5 6 7
U101
1
15
5
3
9
7
13
11
14
6
10
2
16
4
8
12
17
CC2RST
CCCLK_I
VSIM2_I
CCIO
1u
C106
BATT_PWR
CC2CLK_I
VSIM2
VSIM
220n
C108
1n
C109
CCIO
NC
GND
CCCLK
CCRST
CCVCC
X 1 0 3
6
5
4
3
2
1
GND
CC2IO
CC2CLK
CC2RST
GND
VSIM2
GND
VSIM
VSIM_I
CCIO
0 R
R106
0 R
R110
CCCLK
4 k 7
R107
CCIO_I
0 R
R109
CCRST
0 R
R108
CCCLK_I
CCRST_I
BATT+_DSB
0 R
R116
0 R
R117
BATT_RFPA
GND
47u
C111
BATT_PWR
100u
C110
2u2
C116
GND
GND
2u2
C117
3 3 0 k
R120
0 R
R118
BATT_RFPA
100k
R119
GND
100u
C113
GND
GND
100u
C112
BATT_PWR
GND
22u
C114
22u
C115
BATT_RFPA
GND
VSIM2
CC2IO
0 R
R123
0 R
R126
CC2CLK
0 R
R125
CC2RST
0 R
R124
0R
R122
220n
C119
220n
C120
220n
C121
GND
GND
GND
GND
SDIO1
PWM1/SDIO2/GPIO7
DTR0/SDIO_CD/GPIO1
SDIO_CMD
STATUS/SDIO_CLK/GPIO5
GND
220n
C123
VMMC
PLS62-W
X 1 0 2
CD
VSS
D1
D0
CLK
VDD
CMD
D3
D2
X 1 0 4
6
5
4
3
2
1
7
8
9
10 11 12 13
GND
0 R
R121
22p
C122
BATT_PWR
0R
R127
1 0 k
R130
1 0 k
R131
1 0 k
R132
1 0 k
R133
V180
COUNTER/SDIO3/GPIO8
DCD0/SDIO0/GPIO2
VMMC
1 0 k
R134
470R
R128
1 0 k
R129
0R
R135
BATT_RFPA
BATT_RFPA
BATT_RFPA
22p
C124
22p
C125
4u7
C126
10u
C127
GND
LGA-CONNECTOR
p r i n t e d p a r t
( I n p u t : 2 . 8 ~ 4 . 5 V )
Note:
Circuit elements
marked
blue
are not (yet)
populated on the PLS62
evaluation module
boards, and thus re-
served for future use.
