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Field
Name
R/W
Description
CNTUFLG=0.
In the process of reading this register, when CNTUFLG=0
in IWDT_STS register, the read value is valid.
The watchdog timeout cyclecan be calculated by the reload value and
clock prescaled value.
31:12
Reserved
State register (IWDT_STS)
Offset address: 0x0C
Reset value: 0x0000 0000 (not reset in standby mode)
WWDT register address mappin
Table 78 WWDT Register Address Mapping
Register name
Description
Offset address
WWDT_CTRL
Control register
0x00
WWDT_CFG
Configuration register
0x04
WWDT_STS
State register
0x08
WWDT register functional description
These peripheral registers can be operated by half word (16 bits) or word (32
bits).
Control register (WWDT_CTRL)
Offset address: 0x00
Reset value: 0x0000 007F
Field
Name
R/W
Description
6:0
CNT
R/W
Counter Value Setup
This counter is 7 bits, and CNT6 is the most significant bit
These bits are used to store the counter value of the watchdog.
When the count value decreases from 0x40 to 0x3F, WWDT reset will
be generated.
Field
Name
R/W
Description
0
PSCUFLG
R
Watchdog Prescaler Factor Update Flag
When the prescaler factor is updated, it is set to 1 by hardware; after
the prescaler factor is updated, the bit is cleared by hardware; the
prescaler factor is updated only when the PSCUFLG bit is cleared.
1
CNTUFLG
R
Watchdog Counter Reload Value Update Flag
When the counter reload value is updated, it is set to 1 by hardware;
after the counter reload value is updated, the bit is cleared by hardware;
the counter reload value is updated only when the CNTUFLG bit is
cleared.
31:2
Reserved
