GE UR series, Instruction Manual

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GE Multilin L60 Line Phase Comparison System 3-37
3 HARDWARE 3.3 DIRECT INPUT AND OUTPUT COMMUNICATIONS
3
To recover the Rx clock from the data-stream, an integrated DPLL (digital phase lock loop) circuit is utilized. The DPLL is
driven by an internal clock, which is 16-times over-sampled, and uses this clock along with the data-stream to generate a
data clock that can be used as the SCC (serial communication controller) receive clock.
3.3.6 RS422 AND FIBER INTERFACE
The following figure shows the combined RS422 plus Fiber interface configuration at 64K baud. The 7L, 7M, 7N, 7P, and 74
modules are used in two-terminal with a redundant channel or three-terminal configurations where channel 1 is employed
via the RS422 interface (possibly with a multiplexer) and channel 2 via direct fiber.
AWG 24 twisted shielded pair is recommended for external RS422 connections and the shield should be grounded only at
one end. For the direct fiber channel, power budget issues should be addressed properly.
When using a LASER Interface, attenuators may be necessary to ensure that you do not exceed maximum
optical input power to the receiver.
Figure 3–43: RS422 AND FIBER INTERFACE CONNECTION
Connections shown above are for multiplexers configured as DCE (data communications equipment) units.
3.3.7 G.703 AND FIBER INTERFACE
The figure below shows the combined G.703 plus fiber interface configuration at 64 kbps. The 7E, 7F, 7G, 7Q, and 75 mod-
ules are used in configurations where channel 1 is employed via the G.703 interface (possibly with a multiplexer) and chan-
nel 2 via direct fiber. AWG 24 twisted shielded pair is recommended for external G.703 connections connecting the shield to
pin 1a at one end only. For the direct fiber channel, power budget issues should be addressed properly. See previous sec-
tions for additional details on the G.703 and fiber interfaces.
When using a laser Interface, attenuators may be necessary to ensure that you do not exceed the maxi-
mum optical input power to the receiver.
Figure 3–44: G.703 AND FIBER INTERFACE CONNECTION
WARNING
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~
~
~
~
~
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~
Shield
COM
Tx1 +
Tx1 –
Rx1 –
Rx1 +
1a
2b
3a
4b
Fiber
channel 2
Clock
(channel 1)
RS422
channel 1
Surge
1b
2a
3b
6a
8a
Tx2 Rx2
Int
er
-r
elay
comms.
7L
,7M,
7N,
7P
,74
842777A1.CDR
WARNING
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~
~
~
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~
Shield
Tx –
Tx +
Rx –
Rx +
1a
2a
3a
Fiber
channel 2
G.703
channel 1
Surge
1b
2b
3b
Tx2
Rx2
Int
er
-r
elay
communications
7E,
7F
,7G
,
7Q
,75
842778A1.CDR