GE UR Series L90, Instruction Manual

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GE Multilin L90 Line Current Differential System 9-11
9 THEORY OF OPERATION 9.1 OVERVIEW
9
9.1.13 MATCHING PHASELETS
An algorithm is needed to match phaselets, detect lost messages, and detect communications channel failure. Channel fail-
ure is defined by a sequence of lost messages, where the length of the sequence is a design parameter. In any case, the
sequence should be no longer than the maximum sequence number (4 cycles) in order to be able to match up messages
when the channel is assumed to be operating normally.
A channel failure can be detected by a watchdog software timer that times the interval between consecutive incoming mes-
sages. If the interval exceeds a maximum limit, channel failure is declared and the channel recovery process is initiated.
While the channel is assumed to be operating normally, it is still possible for an occasional message to be lost, in which
case fault protection is suspended for the time period that depends on that message, and is resumed on the next occa-
sional message. A lost message is detected simply by looking at the sequence numbers of incoming messages. A lost
message will show up as a gap in the sequence.
Sequence numbers are also used to match messages for the protection computation. Whenever a complete set of current
measurements from all terminals with matching sequence numbers are available, the differential protection function is com-
puted using that set of measurements.
9.1.14 START-UP
Initialization in our peer-to-peer architecture is done independently at each terminal. Relays can be turned on in any order
with the power system either energized or de-energized. Synchronization and protection functions are accomplished auto-
matically whenever enough information is available.
After a relay completes other initialization tasks such as resetting of buffer pointers and determining relay settings, initial
values are computed for any state variables in the loop filters or the protection functions. The relay starts its clock at the
nominal power system frequency. Phaselet information is computed and transmitted.
• Outgoing messages over a given channel are treated in the same way as during the channel recovery process. The
special start-up message is sent each time containing only a single time step value.
• When incoming messages begin arriving over a channel, that channel is placed in service and the loop filters are
started up for that channel.
• Whenever the total clock uncertainty is less than a fixed threshold, the phase locking filter is declared locked and differ-
ential protection is enabled.
9.1.15 HARDWARE AND COMMUNICATION REQUIREMENTS
The average total channel delay in each direction is not critical, provided the total round trip delay is less than 4 power sys-
tem cycles. The jitter is important, and should be less than ±130

s in each direction. The effect of a difference in the aver-
age delay between one direction and the other depends on the number of terminals. In the case of a 2 or 3 terminal system,
the difference is not critical, and can even vary with time. In the case of a 4 or more terminal system, variation in the differ-
ence limits the sensitivity of the system.
• The allowable margin of 130

s jitter includes jitter in servicing the interrupt generated by an incoming message. For
both incoming and outgoing messages, the important parameter is the jitter between when the time stamp is read and
when the message begins to go out or to come in.
• The quality of the crystal driving the clock and software sampling is not critical, because of the compensation provided
by the phase and frequency tracking algorithm, unless it is desired to perform under or over frequency protection.
From the point of view of current differential protection only, the important parameter is the rate of drift of crystal fre-
quency, which should be less than 100 parts per million per minute.
• A 6 Mhz clock with a 16-bit hardware counter is adequate, provided the method is used for achieving the 32-bit resolu-
tion that is described in this document.
• An 8-bit time stamp is adequate provided time stamp messages are exchanged once per cycle.
• A 4-bit message sequence number is adequate.