GE PCIE-5565PIORC*, Hardware Reference Manual

Page: 37 / 70

Programming 37
Table 3-17 PCI Cardbus CIS Pointer Register
PCI Cardbus CIS Pointer: Offset $28
Bit Description Read Write
Value after
PCI Reset
31:0 Cardbus Information Structure Pointer for PCMCIA . Not Supported. Yes No $0
Table 3-18 PCI Subsystem Vendor ID Register
PCI Subsystem Vendor ID: Offset $2C
Bit Description Read Write
*Value after
PCI Reset
15:0 Subsystem Vendor ID (unique add-in board Vendor ID). Yes No $1556
* NOTE : The value $1556 denotes a PLD Application.
Table 3-19 PCI Subsystem ID Register
PCI Subsystem ID: Offset $2E
Bit Description Read Write
*Value after
PCI Reset
15:0 Subsystem ID (unique add-in board device ID). Yes No $0080
* NOTE : The value $0080 denotes a PLD Application PCI-X core.
Table 3-20 PCI Expansion ROM Base Register
PCI Expansion ROM Base: Offset $30
Bit Description Read Write
*Value after
PCI Reset
0 Address Decode Enable.
A one (1) indicates a device accepts accesses to the Expansion ROM address.
A zero (0) indicates a device does not accept accesses to Expansion ROM
space. Should be set to zero (0) if there is no Expansion ROM. Works in
conjunction with EROMRR[0].
Yes No 0
10:1 Reserved Yes No $0
31:11 Expansion ROM Base Address (upper 21 bits). Yes Yes $0
* NOTE : PCI Expansion ROM and related registers are not applicable to the Reflective Memory.
Table 3-21 PCI Capability Pointer Register
Capability Pointer: Offset $34
Bit Description Read Write
Value after
PCI Reset
7:0 New Capability Pointer. Offset into PCI Configuration Space for the location
of the first item in the New Capabilities Linked List.
Yes No $78
31:8 Reserved Yes No $0