GE Mini COM Express 10, Hardware Reference Manual

Page: 58 / 82

6.7.4 Interrupt Identification
This register provides the status and source of the highest-priority pending UART
interrupt.
The various UART interrupt indications are cleared in different manners, depending upon
the source of the interrupt. A receiver line status interrupt is cleared by reading the Line
Status register. The receiver data available interrupt is cleared by reading the Receive
Buffer register, or when the FIFO falls below the trigger level. The timeout interrupt is
cleared by reading from the FIFO. A transmit holding register empty interrupt is cleared
either by reading the Interrupt Identification Register (when it is the source of the
interrupt) or by writing to the Transmit Data register. A modem status interrupt is cleared
by reading the Modem Status register. Receive and transmit DMA interrupts are cleared
by reading the Interrupt Identification Register when they are the source of the interrupt.
UART Interrupt Identification Register (Offset 0x2)
Bit Name Access Default
Description
7:06 FIFO R 0b00 Set to 0b11 when FIFO mode is enabled
5:0
TX_DMA
R 0
Transmit DMA transfer complete. The interrupt ID will be
0b001.
4:0
RX_DMA
R 0
Receive DMA transfer complete. The interrupt ID will be
0b010.
3:01 ID R 0b000
Highest priority interrupt identification
0b011 (1st): receiver line status
0b010 (2nd): receiver data available
0b110 (2nd): timeout indication (FIFO mode only)
0b001 (3rd): transmit holding register empty
0b000 (4th): modem status
0:0 NPEND R 1
When 0, indicates an interrupt is pending
58 GFK-2896 Mini COM Express Type 10 Module mCOM10-L1500
For public disclosure