GE MAC 5500, Service Manual

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Revision E MAC

5500 resting ECG analysis system 2-13

2020299-020
Equipment Overview: Theory of Operation
CPU (Stooges)
Each of the three Stooges has its own 4 Mhz ceramic resonator for use in generating
their respective clocks.
RTC
The Real Time Clock of the system is provided as a part of the Super I/O controller.
The timing for this function is derived from its own 32.768 Khz crystal.
CPU
The ATMEL AT91RM9200 replaces the Strong ARM SA1110 used in -005 board.
The AT91RM9200 uses high performance, low power consumption and high code
density ARM920T processor core. One of the major difference between SA1110
and AT91RM9200 is the absence of built in LCD controller and 16-bit static
memory controller. StrongARM support 32 bit memory interface. The Processor
Clock and External Bus speed is limited to 180 and 80 MHz when compare with the
206 and 103 MHz of StrongARM. Having an external LCD controller with a
separate video memory interface compensates overall performance of the CPU.
External Bus Interface
The external bus interface width is limited to 16bit in ATMEL CPU when compare
with the 32 bit interface of StrongARM. All the non VGA FPGA registers are
either 8 bit or 16 bit wide. However all these were accessed using 32 bit access in
-005 board and aligned to 32 bit word. To port the applications that was written for
the 32 bit access, all the Non VGA memory space within the FPGA are accessed in
32 bit mode in -006 board. When the ATMEL static memory controller see a 32 bit
memory access, it perform two consecutive 16 bit access. To avoid over writing of
FPGA register with upper 16-Byte data, The FPGA register access logic is designed
in such a way that, the FPGA ignores upper 16 byte access. However for access to
the pixel data FIFO, the upper 16 bit contains valid data and the this will be loaded
into the next 16 bit word.
The VGA registers are accessed using 32 bit access. The Frame Buffer area can be
accessed either in 32 bit word mode or byte mode.