GE L60, Instruction Manual, Page: 358 / 498

8-18 L60 Line Phase Comparison Relay GE Multilin
8.1 OVERVIEW 8 THEORY OF OPERATION
8
8.1.6 SINGLE VS. DUAL PHASE COMPARISON
In all the phase comparison schemes described so far, a trip attempt is made only every other half cycle. In the examples
illustrated, this was every positive half cycle. Such schemes are termed single phase-comparison as against dual phase-
comparison where a trip attempt is made every half cycle, positive and negative.
The only advantage of dual-comparison is that its maximum operating time to trip on internal faults will be a half cycle faster
than the maximum time for the single phase-comparison. The minimum times for both schemes will be the same. This dif-
ference in maximum time results because a fault could occur at such an instant in time when the current is just going nega-
tive. Under such conditions, the single phase-comparison would have to wait till the next positive half cycle while the dual
phase-comparison could trip on the upcoming negative half cycle.
While, as a general rule, high speed operation and security are on opposite sides of the coin, it is possible to design dual
phase-comparison schemes that can provide the added speed with little or no loss in security. However, these schemes are
somewhat more complex than equivalent single phase-comparison schemes. Figure 8-13 illustrates the dual phase-com-
parison tripping scheme that is the counterpart of the single phase-comparison scheme of Figure 8-11. The differences are
noted below.
1. The dual scheme uses two separate comparer integrator combinations, one for the positive half cycle and the other for
the negative half cycle.
2. A three-frequency, frequency-shift channel is used in dual phase comparison. The high-shift operates in conjunction
with the positive half cycle while the low-shift works with the negative half cycle. When the channel is not keyed to
either high or low, it operates on the center frequency. There is no center frequency output from the receiver into the
relay tripping logic.
3. AND3 is included to make it impossible to key both frequencies simultaneously. It also gives preference to the low-shift
which is sent continuously when FDL is dropped out. Thus, on single-end feed tripping can take place only on the neg-
ative half cycle.
Figure 8–13: DUAL PHASE COMPARISON TRIPPING SCHEME