GE IMP2B, Hardware Reference Manual

Page: 35 / 55

Publication No. IMP2B-0HH/5 Functional Description 35
In the following registers, GPIO line/pin to bit mapping is as follows:
Table 3-23 GPIO Line to Register Bit Mapping
Bits Line
0 GPIO(0)
1 GPIO(1)
2 GPIO(2)
3 GPIO(3)
15 to 4 Reserved
3.16.1 GPIO Direction Control Register – Offset 0x00000400
The bits indicate the direction of the corresponding GPIO line, as follows:
0 = Input (default)
1 = Output
3.16.2 GPIO Data Register – Offset 0x00000402
The bits hold the data for or from the corresponding GPIO line.
If the line is set as input (read only):
0 = Line is low
1 = Line is high
If the line is set as output (read/write):
0 = Line is driven low
1 = Line is driven high
3.16.3 GPIO Polarity Control Register – Offset 0x00000404
The bits indicate the polarity of the corresponding GPIO line, as follows:
0 = Active high (default)
1 = Active low
3.16.4 GPIO Interrupt Mode Register – Offset 0x00000406
The bits indicate the interrupt mode of the corresponding GPIO line, as follows:
0 = Edge triggered (rising)
1 = Level triggered [default]