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22 IMP2B 3U cPCI Single Board Computer

Publication No. IMP2B-0HH/5

3.7.1

PMC Rear I/O Tracking

The PMC site J14 pins 1 to 49 (or 1 to 64 in ‘Peripheral Only’ or ‘Limited Host, Full
PMC User I/O’ modes) are not mapped according to the conventional PMC Pn4 to
cPCI J2 scheme. The routing pattern used by the IMP2B is biased towards PMC cards
that use the Pn4 connector pins in pairs (1-3, 2-4, 5-7, 6-8, etc.) The signals are tracked
as 50 Ω single-ended to Ground and not as matched pairs (or triples). Sets of four
pairs (1 to 8, 9 to 16 … 40 to 48 in Host mode, or 56 to 64 in ‘Peripheral Only’ and
‘Limited Host, Full PMC User I/O’ modes) are matched in length, but no two sets of
four pairs are the same length (e.g. 1 to 8 are all the same length, and 9 to 16 are all
the same length, but 1 to 8 are not the same length as 9 to 16). See the

description for the PMC user rear I/O pinout.

3.7.2

‘Peripheral Only’ Mode

The IMP2B supports a build of ‘Peripheral Only’ mode as a build option. In this
configuration, all 64 lines of PMC User I/O are routed to the cPCI

, but

the ability of the IMP2B to operate as a cPCI Rack Host is sacrificed.

CAUTION

Do not install an IMP2B built in ‘Peripheral Only’ mode into a Rack Host cPCI slot.

3.7.3

‘Limited Host, Full PMC User I/O’ Mode

The IMP2B supports a build of ‘Limited Host, Full PMC User I/O’ mode as a build
option. This allows the IMP2B to both operate as a Rack Host, supporting up to three
cPCI Slave cards,

and

provide access to all 64 PMC user I/O lines via the cPCI

. This mode is primarily intended to be used in custom backplanes

designed specifically to support this configuration.

CAUTION

If an IMP2B built in this mode is to be used in the Host slot of a commercial rack, take extra care, as

some PMCs may have their I/O connected to backplane traces that they are not designed to drive (i.e.

GND or cPCI REQs, GNTs or CLKs).

In this mode, the IMP2B uses the cPCI Geographical Address bits (3:0) to determine
whether it is to operate as a Rack Host, as the more usual SYSEN~ signal is re-
designated as a PMC User I/O signal.

The Spare link (

) determines the Geographical Address that is required to

enable Rack Host mode. With the link out, a Geographical Address of (3:0) = 0101

b

selects Host mode. With the link in, a Geographical Address of (3:0) = 0001

b

selects

Host mode.

NOTE

Geographical Address Bit (4) is unused.

In a Host slot, an IMP2B supports up to three cPCI Slaves at 33 or 66 MHz, 3.3 V VIO
only.

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Summary of Contents for IMP2B

Page 1: ...GE Intelligent Platforms Hardware Reference Manual IMP2B 3U cPCI Single Board Computer Edition 5 Publication No IMP2B 0HH 5 ...

Page 2: ...d Electronic Equipment WEEE Returns GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our customers before Augus...

Page 3: ...ains hardware information for the IMP2B boards with PCB artwork revisions 4 and onwards The information contained in this manual must be used in conjunction with the PowerPact3 Family Product Manual LINK PowerPact3 Family Product Manual publication number PP3 0HH ...

Page 4: ... Link P5 1 2 14 2 12 NVRAM Serial EEPROM Write Enable Link P5 3 4 15 2 13 Spare Link P5 5 6 15 2 14 Special Linking Requirements 15 3 Functional Description 16 3 1 PowerPC Processor 16 3 2 Host Bridge 17 3 3 RAM 18 3 4 Non Volatile RAM NVRAM 18 3 5 Flash Memory 19 3 5 1 Boot Flash 19 3 5 2 User Flash 20 3 5 3 Flash Sector Protection 20 3 6 Memory Map set up by VxWorks as seen by CPU 21 3 7 PMC Sit...

Page 5: ... 0x00000400 35 3 16 2 GPIO Data Register Offset 0x00000402 35 3 16 3 GPIO Polarity Control Register Offset 0x00000404 35 3 16 4 GPIO Interrupt Mode Register Offset 0x00000406 35 3 16 5 GPIO Interrupt Active Register Offset 0x00000408 36 3 16 6 GPIO Interrupt Enable Register Offset 0x0000040A 36 3 16 7 GPIO Masked Interrupt Status Register Offset 0x0000040C 36 3 17 CompactPCI Arbiter 36 3 18 Resets...

Page 6: ... Per Port in Available Modes 24 Table 3 8 I2C Device Addresses 26 Table 3 9 EPLD Registers 28 Table 3 10 Board ID Register 1 29 Table 3 11 Board ID Register 2 29 Table 3 12 Device Bus Information Register 1 29 Table 3 13 Device Bus Information Register 2 30 Table 3 14 Configuration Register 1 30 Table 3 15 Configuration Register 2 31 Table 3 16 Control Register 1 31 Table 3 17 Control Register 2 3...

Page 7: ...46 Table 4 6 J2 Signal Descriptions 47 Table A 1 Technical Specification 48 Table A 2 Voltage Supply Requirements 49 Table A 3 Power Dissipation 49 Table A 4 Reliability MTBF 50 Table A 5 Product Codes 51 List of Figures Figure 1 1 View of IMP2B 9 Figure 2 1 Link Positions Top 10 Figure 3 1 Block Diagram 16 Figure 3 2 RS422 485 Signal Definition 24 Figure 3 3 LED Positions 40 Figure 3 4 Front Pane...

Page 8: ... Up to 256 MBytes of Spansion Flash memory 128 MBytes as standard 128 KByte AutoStore NVRAM 32 bit 66 MHz CompactPCI interface 3 3 V signaling only 64 bit 133 MHz PCI X to PMC site 3 3 V signaling only 1 to 49 PMC user rear I O 1 to 64 if built in Peripheral Only or Limited Host Full PMC User I O modes Two serial ports software configurable for RS232 RS422 asynchronous only One 10 100 1000BaseT or...

Page 9: ...Publication No IMP2B 0HH 5 Overview 9 Figure 1 1 View of IMP2B ...

Page 10: ...section s in the following pages Figure 2 1 Link Positions Top 2 1 Link Functions Table 2 1 Link Functions Link Pins Function Link Pins Function P5 5 6 Spare P3 5 6 User Flash write enable 3 4 NVRAM write enable 3 4 Boot Flash write enable 1 2 Force CPCI 33 MHz operation 1 2 Flash protection password unlock P4 5 6 Backplane JTAG AutoWrite enable P2 5 6 Backplane Flash programming 3 4 Backplane JTA...

Page 11: ... 2 3 Factory Test Link P1 This link is for factory test use only and should not be fitted 2 4 Flash Boot Image Select Links P2 1 2 and 3 4 The Boot Flash is divided into four sections with all sections accessible all of the time This allows for three user boot images to be stored in the Flash along with a factory programmed recovery boot image Using these links the four sections can be swapped aro...

Page 12: ...ion In Backplane Flash Programming mode 2 6 Flash Protection Password Unlock Link P3 1 2 Fitting a jumper across this link allows software to read the password used to disable the persistent mode sector protection which remains unchanged following a reset or a power cycle See the Flash Sector Protection section for further details Not fitting a jumper prevents the software from altering any previo...

Page 13: ...ks now have no effect on the hardware interface to the Flash devices as all sector protection is controlled by software See the Flash Sector Protection section for further details NOTE After the boot sequence user software may alter sector protection at any time Table 2 6 Links P3 3 4 and 5 6 Link Meaning Out Boot User Flash sectors are write protected by default In Boot User Flash sectors are wri...

Page 14: ...he JTAG Technologies Flash Programming equipment from the backplane to the JTAG Scanbridge device Table 2 9 Link P4 5 6 Link Function Out Backplane JTAG AutoWrite signal not connected In Backplane JTAG AutoWrite signal connected NOTE The AutoWrite signal is allocated to a bused reserved pin A5 on connector J1 This link allows the signal to be disconnected if this pin is not being used for this pur...

Page 15: ...n NVRAM writes enabled NOTE This link write enables the I2C EEPROM in conjunction with a bit in the EPLD Control Register 1 2 13 Spare Link P5 5 6 This link is reserved for future use Its status may be read back in the EPLD Configuration Register 1 Also see the Limited Host Full PMC User I O Mode section 2 14 Special Linking Requirements For deployed use any of the nine links on P3 P4 and P5 can b...

Page 16: ...a bus On chip 32 KByte L1 instruction and data caches On chip 1 MByte L2 cache running at core frequency Altivec Vector Unit Enhanced branch prediction capabilities MMU and integral FPU The processor implements a fully static architecture and offers sophisticated power management capabilities including Dynamic Frequency Switching Dynamic Power Management and Instruction Cache Throttling More infor...

Page 17: ...ace PCI1 PCI X interface to PMC site PCI0 DDR2 SDRAM memory controller Device Bus interface to Flash NVRAM and EPLD devices Two 10 100 1000BaseT Ethernet MACs Two USB 2 0 host ports OHCI EHCI Two RS232 422 asynchronous serial channels Four IDMA engines Two XOR DMA engines Four 32 bit timers Watchdog timer Interrupt handler I2C Bus interface NOTE At the time of writing Discovery MV64560 data is und...

Page 18: ...orrecting single bit errors CAUTIONS The second DDR2 RAM bank physically resides in the PMC Keep Out area When the IMP2B is fitted with 1 GByte of DRAM memory the available component height in the PMC Keep Out region for an install PMC is reduced from 10mm to 5mm Integrity of SDRAM data cannot be guaranteed during hard reset since the memory controller is reset and SDRAM refresh disabled 3 4 Non V...

Page 19: ...nization 128 2 2 x 512Mbit 256 2 2 x 1024Mbit The Flash is divided into two areas Boot Flash and User Flash The top 8 MBytes of the first bank are reserved as Boot Flash The remainder of the Flash memory is allocated as User Flash NOTE Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle 3 5 1 Boot Flash The Boot Flash in the top 8 MBytes of Flash memory h...

Page 20: ...rotected or unlocked write enabled by writing to configuration registers within the Flash The configuration of this protection is only possible when the Flash Protection Password Unlock Link P3 1 2 is fitted If no jumper is fitted on this link the software is unable to change the sector protection and those sectors that are locked may not be erased or reprogrammed under any circumstances 2 Non per...

Page 21: ...7 PMC Site The PMC site is connected to the PCI0 port of the MV64560 This bus supports 32 or 64 bit data widths and bus speeds up to 133 MHz It is capable of using the PCI X protocol but is backward compatible with standard PCI The PMC bus speed can be read from the EPLD Device Bus Information Register 1 Only PMC cards that operate using 3 3 Volt signaling VIO are supported CAUTION Fitting a PMC d...

Page 22: ...sacrificed CAUTION Do not install an IMP2B built in Peripheral Only mode into a Rack Host cPCI slot 3 7 3 Limited Host Full PMC User I O Mode The IMP2B supports a build of Limited Host Full PMC User I O mode as a build option This allows the IMP2B to both operate as a Rack Host supporting up to three cPCI Slave cards and provide access to all 64 PMC user I O lines via the cPCI J2 connector This mo...

Page 23: ... E5 GNT5 J2 E15 GNT6 J2 E17 3 7 4 Alternative PMC I O Mode The IMP2B supports a build of Alternative PMC I O mode as a build option This allows four of the PMC I O not normally available in Host mode to be made available When this option is selected PMC I O 45 48 are replaced by PMC I O 61 64 See section 4 1 4 for the J2 connector pinout Table 3 6 Alternative PMC I O Mode Signals J2 Pin IMP2B xxxx...

Page 24: ...s single ended RS232 for use as a debug port Both ports are disabled at power up Table 3 7 Signal Sets Per Port in Available Modes RS232 RS422 TXD TX_A RTS TX_B RXD RX_A CTS RX_B For RS422 outputs the non inverting output of the differential pair is designated B and the inverting output is designated A Figure 3 2 RS422 485 Signal Definition The ports use a single Intersil IS41334 transceiver and a...

Page 25: ...ch port has a software enabled power controller capable of providing up to 0 5 Amps of power at 5 0 V For more details see the EPLD Control Register 1 3 11 Timers The MV64560 provides four 32 bit timer counters that operate at a frequency of 133 MHz and have a resolution of 7 5 ns There is an option for software to cascade two timers to form a 64 bit timer counter This is done by connecting the te...

Page 26: ...PROM PCF8563 0xA2 Real Time Clock DS1682 0xD6 Elapsed Time Indicator 3 14 1 Serial EEPROM An 8 KByte Serial EEPROM is provided for non volatile data storage The device is write protected by default and can be write enabled by fitting the NVRAM Serial EEPROM Write Enable Link P5 3 4 and by clearing the appropriate bit in the EPLD Control Register 1 NOTE Integrity of EEPROM data cannot be guaranteed...

Page 27: ...re shipping and the device set to read only For more details see the device data sheet LINK http www maxim ic com quick_view2 cfm qv_pk 2756 3 14 4 Temperature Sensing The IMP2B has two temperature sensors An LM92 is used to measure the ambient board temperature and an ADT7461 is used to measure the CPU junction temperature Both are capable of generating interrupts on either high or low ranges LIN...

Page 28: ...rmation Register 2 0x00000008 Configuration Register 1 0x0000000A Configuration Register 2 0x0000000C Control Register 1 0x0000000E Control Register 2 0x00000010 Test Register 1a 0x00000012 Test Register 1b 0x00000014 Test Register 2a 0x00000016 Test Register 2b 0x00000018 Test Register 3a 0x0000001A Test Register 3b 0x0000001C Scratchpad Register 1 0x0000001E Scratchpad Register 2 0x00000020 EPLD...

Page 29: ...n Register 1 Offset 0x00000004 Table 3 12 Device Bus Information Register 1 Bits Mode Description Notes 2 to 0 Read only CompactPCI bus speed 000 PCI 33 MHz 001 PCI 66 MHz 3 Reserved 6 to 4 Read only PMC bus speed 000 PCI 33 MHz 001 PCI 66 MHz 100 PCI X 66 MHz 101 Reserved 110 PCI X 133 MHz 7 Read only PMC I O voltage 0 3 3 V hardwired 9 8 Read only Flash device size 00 1 Gbit 01 2 Gbit planned 10...

Page 30: ...ead only Flash Protection Password Visible Link 0 Not fitted 1 Fitted 1 Read only Boot Flash Write Enable Link 2 Read only User Flash Write Enable Link 3 Reserved 4 Read only Select Alternate Boot Image Link 0 Not fitted 1 Fitted 5 Read only Select Recovery Boot Image Link 6 Read only Backplane Flash programming 0 Disabled 1 Enabled 7 Read only BIT Fast Start 0 Disabled 1 Enabled 8 Read only Spare...

Page 31: ...ite protection 0 I2C EEPROM writable 1 I2C EEPROM write protected default requires the NVRAM Write Enable Link P5 3 4 to be fitted to write a 0 1 Read Write COM1 Transceiver Driver Skew Control A 0 COM1_SPA low default 1 COM1_SPA high 2 Read Write COM1 Transceiver Driver Skew Control B 0 COM1_SPB low default 1 COM1_SPB high 3 Reserved 4 Read Write cPCI Arbiter Mode 0 Fixed Priority 1 Round Robin d...

Page 32: ...a 0x00000010 15 to 0 Read only Test pattern 0xAAAA Displays the second 16 bits of the Flash Protection Password if the Flash Protection Password Unlock Link P3 1 2 is fitted Test 1b 0x00000012 15 to 0 Read only Test pattern 0xAAAA Displays the first 16 bits of the Flash Protection Password if the Flash Protection Password Unlock Link P3 1 2 is fitted Test 2a 0x00000014 15 to 0 Read only Test patte...

Page 33: ... Port 1 Overload interrupt 7 Read only Reserved Returns 0 8 Read Write RTC Interrupt mask 0 Enabled 1 Masked default 9 Read Write Temperature Interrupt mask 10 Read Write Temperature Critical Interrupt mask 11 Read Write PHY0 Interrupt mask 12 Read Write PHY2 Interrupt mask 13 Read Write USB Port 0 Overload Interrupt mask 14 Read Write USB Port 1 Overload Interrupt mask 15 Read Write Software gene...

Page 34: ...red as either an input or an output and its value can be read or written as appropriate Each pin may be assigned a polarity either active high or active low which determines how the registers display its active state Each input signal is capable of generating an interrupt to the MV64560 interrupt controller Each signal can be configured as level or edge sensitive and can be masked as required Edge...

Page 35: ...GPIO Data Register Offset 0x00000402 The bits hold the data for or from the corresponding GPIO line If the line is set as input read only 0 Line is low 1 Line is high If the line is set as output read write 0 Line is driven low 1 Line is driven high 3 16 3 GPIO Polarity Control Register Offset 0x00000404 The bits indicate the polarity of the corresponding GPIO line as follows 0 Active high default...

Page 36: ...abled 3 16 7 GPIO Masked Interrupt Status Register Offset 0x0000040C This read only register is a logical AND of the GPIO Interrupt Active and GPIO Interrupt Enable Registers The bits indicate whether interrupts on the corresponding GPIO line are active and enabled as follows 0 Interrupt inactive or disabled 1 Interrupt active and enabled 3 17 CompactPCI Arbiter The EPLD contains an 8 slot PCI arb...

Page 37: ...eset Hard reset all devices if Peripheral card Software Generated reset Hard reset all devices If the IMP2B is configured as the System Controller Rack Host then a hard reset causes the CompactPCI backplane reset to be driven active resetting all peripheral cards in the system The cause of a reset is latched in the EPLD Configuration Register 1 CAUTION Integrity of SDRAM data cannot be guaranteed ...

Page 38: ... INT MPP 19 Derives from the EPLD from the interrupts sources below GPIO INT MPP 21 Derives from the GPIO block within the EPLD The EPLD combines the following interrupts to produce EPLD INT Table 3 26 Interrupt Combination Interrupt Source Cause RTC_INT Real Time Clock TEMP_INT Ambient sensor or CPU junction temperature sensor Temperature TEMP_CRT Ambient sensor or CPU junction temperature sensor...

Page 39: ...LD 6 Accelerated Flash Programming The input to the Scanbridge is driven from the CompactPCI JTAG signals as defined by PICMG2 0 Rev 3 0 NOTE In PICMG 2 0 Rev 3 0 it is recommended that the Backplane JTAG signals are not used When no jumper is fitted across link P4 3 4 the IMP2B does not drive these pins and so these signals may be used for any other purpose allocated to them A separate COP header...

Page 40: ...ffic DS255 Yellow Ethernet Channel 0 Transmit Traffic DS256 Yellow Ethernet Channel 1 10BaseT DS257 Yellow Ethernet Channel 1 100BaseT DS258 Yellow Ethernet Channel 1 1000BaseT DS259 Yellow Ethernet Channel 1 Duplex DS260 Yellow Ethernet Channel 1 Receive DS261 Yellow Ethernet Channel 1 Transmit DS262 Green Power Good DS263 Red BIT Fail DS264 Yellow BIT LED 1 DS265 Yellow BIT LED 2 DS266 Green BIT...

Page 41: ...tus of BIT as follows Table 3 29 BIT Status LEDs BIT Fail LED DS263 BIT Passed LED DS266 Status Lit Unlit BIT not run Reset state or BIT Failed Unlit Lit BIT complete and passed If BIT fails then DS264 and DS265 are illuminated to provide debug information 3 22 Front Panel Figure 3 4 Front Panel ...

Page 42: ...hows the function of the connectors on the IMP2B Table 4 1 Connector Functionality Connector Function J1 CompactPCI bus see general description J2 CompactPCI bus system and I O J11 J12 J13 J14 PMC1 site see general description P38 JTAG test header for use with IMP2AJTAG Figure 4 1 Connector Positions ...

Page 43: ... GND 8 J14 24 J14 23 J14 28 J14 27 J14 31 GND 7 J14 30 J14 34 J14 33 J14 38 J14 37 GND 6 J14 32 J14 36 J14 35 J14 40 J14 39 GND 5 J14 49 J14 42 J14 41 J14 46 J14 45 GND 4 Unused J14 44 J14 43 J14 48 J14 47 GND 3 CLK4 GND GNT3 REQ4 GNT4 GND 2 CLK2 CLK3 SYSEN GNT2 REQ3 GND 1 CLK1 GND REQ1 GNT1 REQ2 GND Non I O signals in grey above are described in more detail in the PowerPact3 Family Product Manual...

Page 44: ... J14 37 GND 6 J14 32 J14 36 J14 35 J14 40 J14 39 GND 5 J14 49 J14 42 J14 41 J14 46 J14 45 GND 4 J14 51 J14 44 J14 43 J14 48 J14 47 GND 3 J14 50 J14 54 J14 53 J14 58 J14 57 GND 2 J14 52 J14 56 J14 55 J14 60 J14 59 GND 1 No Connection J14 62 J14 64 J14 61 J14 63 GND Non I O signals in grey above are described in more detail in the PowerPact3 Family Product Manual LINK PowerPact3 Family Product Manua...

Page 45: ...49 J14 42 J14 41 J14 46 J14 45 GND 4 J14 51 J14 44 J14 43 J14 48 J14 47 GND 3 J14 50 J14 54 J14 53 J14 58 J14 57 GND 2 J14 52 J14 56 J14 55 J14 60 J14 59 GND 1 No Connection J14 62 J14 64 J14 61 J14 63 GND Non I O signals in grey above are described in more detail in the PowerPact3 Family Product Manual LINK PowerPact3 Family Product Manual publication number PP3 0HH Key PMC rear I O signals see t...

Page 46: ... J14 23 J14 28 J14 27 J14 31 GND 7 J14 30 J14 34 J14 33 J14 38 J14 37 GND 6 J14 32 J14 36 J14 35 J14 40 J14 39 GND 5 J14 49 J14 42 J14 41 J14 61 J14 62 GND 4 Unused J14 44 J14 43 J14 63 J14 64 GND 3 CLK4 GND GNT3 REQ4 GNT4 GND 2 CLK2 CLK3 SYSEN GNT2 REQ3 GND 1 CLK1 GND REQ1 GNT1 REQ2 GND Non I O signals in grey above are described in more detail in the PowerPact3 Family Product Manual LINK PowerPa...

Page 47: ...ins 1 to 49 or 1 to 64 in Peripheral Only or Limited Host Full PMC User I O modes are not mapped according to the conventional PMC Pn4 to cPCI J2 scheme The routing pattern used by the IMP2B is biased towards PMC cards that use the Pn4 connector pins in pairs 1 3 2 4 5 7 6 8 etc The signals are tracked as 50 Ω single ended to Ground not as matched pairs or triples Sets of four pairs 1 to 8 9 to 16...

Page 48: ... MV64560 provides 1 or 2 Ethernet channels accessed through the J2 connector USB 2 0 Host Ports OHCI EHCI compliant Individual software enabled power controllers 0 5 A each Serial ports 2 x RS232 422 ports MV64560 provides 2 serial channels both software selectable to be RS232 or RS422 asynchronous only Discrete Digital I O 4 bits TTL compatible 4 bits of GPIO each bit being capable of generating ...

Page 49: ...nd maximum figures running a Fast Fourier Transform test at 85 C to push the processor toward its maximum power output Table A 3 Power Dissipation Processor Frequency MHz Bus Frequency MHz Processor Core Voltage V Typical Power W Maximum Power W 1400 200 1 15 17 W 25 C 3 1 A 5 V 0 5 A 3 3 V 27 5 W 85 C 5 0 A 5 V 0 7 A 3 3 V 1400 Nap enabled 200 1 15 7 5 W 25 C 27 5 W 85 C 5 0 A 5 V 0 7 A 3 3 V 100...

Page 50: ...ed 40 c 10 98314 91 049 Naval unsheltered 45 c 20 33436 49 178 Airborne inhabited cargo 55 c 14 58733 68 553 Airborne inhabited fighter 55 c 18 52974 53 967 Airborne uninhabited cargo 70 c 27 58463 36 252 Airborne uninhabited fighter 70 c 40 27936 24 827 Airborne rotary wing 55 c 29 85988 33 490 Space flight 30 c 2 17541 459 684 Missile flight 45 c 35 67331 28 032 Missile launch 55 c 84 5206 11 83...

Page 51: ...Hz consult factory 4 7448 1 GHz low power variant 1 Level 1 2 Level 2 3 Level 3 4 Level 4 5 Level 5 9 Level 9 55 C to 85 C consult factory before ordering NOTE Not all options or combinations of options are available Please consult your local GE Intelligent Platforms sales office for full ordering information A 6 Software Support VxWorks Tornado BSP IMPBSP TOR2M VxWorks Tornado ESP IMPBESP TOR2M W...

Page 52: ...nnector and brings out the following groups of signals COM1 COM2 RS232 COM1 RS422 COM2 RS422 10 100 BaseT or 10 100 1000BaseT Ethernet Channel 0 Link configured 10 100BaseT Ethernet Channel 1 if Channel 0 is not linked for 10 100 1000BaseT Ethernet USB2 0 Port 0 and 1 4 GPIO lines PMC Rear I O signals 1 to 49 50 to 64 are optional and link controlled The CPCI3UX605 is compliant with the IEEE1101 1...

Page 53: ...M 26 Write Enable 15 Elapsed Time Indicator 27 Electrical Specification 49 EPLD 28 Ethernet 25 F Fast BIT 34 Fast Start 34 Features 8 Flash 19 Backplane Programming 12 Boot 19 Password Unlock 12 Sector Protection 20 User 20 Write Enabling 13 Force CPCI 33 MHz Operation 14 Front Panel 41 Functional Description 16 G GPIO Controller 34 H Host Bridge 17 I I O Modules 52 I2C Interface 26 Interrupts 33 ...

Page 54: ...on 2 31 Control 1 31 Control 2 32 Device Bus Information 1 29 Device Bus Information 2 30 EPLD Interrupt 33 R continued Registers continued GPIO Data 35 Direction Control 35 Interrupt Active 36 Interrupt Enable 36 Interrupt Mode 35 Masked Interrupt Status 36 Polarity 35 Scratchpad 32 Semaphore 34 Software Reset 33 Test 32 Reliability 50 Resets 37 S SDRAM 18 Serial Ports 24 Software Support 51 Spec...

Page 55: ...TIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia Pacific 86 10 6561 1561 Europe Middle East ...

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