Gateway 910 Series, System Manual

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Reference Data
Interrupts
The following table suggests a logical interrupt mapping of interrupt sources.
It reflects a typical configuration, but you can change these interrupts. Use
the information to determine how to program each interrupt. The actual
interrupt map is defined using configuration registers in the I/O controller.
I/O Redirection Registers in the I/O APIC are provided for each interrupt
signal. The signals define hardware interrupt signal characteristics for APIC
messages sent to local APIC(s).
Interrupt System Resource
NMI I/O channel check
0 Reserved, interval timer
1 Reserved, keyboard controller
2 Reserved, cascade interrupt from slave PIC
3 COM2*
4 COM1*
5 USB
6 Floppy controller
7 LPT1*
8 Real-time clock
9 Reserved for ACPI SCI
10 User available
11 User available
12 Onboard mouse port (if present, otherwise user available)
13 Reserved, system interrupt/FERR
14 Primary IDE (if present, otherwise user available)
15 Secondary IDE (if present, otherwise user available)
* This setting is the default, but it can be changed in the BIOS Setup utility.