SK-MB9EF120-002,-003
Configuration and Test-Points
UG-9E0010-11
- 16 -
© Fujitsu Semiconductor Europe GmbH
4.3 Test-Points
Testpoints are not for permanent connection, but mostly for failure-tracking. Normally, there is no
need to access them.
Name
Label
Description
Position
TP6
SubClk
input of 32768Hz crystal-oscillator (RTC, etc.).
top F-9
TP5
MainClk
main clock reference crystal (Q1).
top E/F-8
TP1
SYSC_CKOT
MCU-port P0_41 which can have this signal multiplexed on its
output.
top H/I-5/6
TP2
SYSC_CKOT
X
MCU-port P0_42 which can have this signal multiplexed on its
output.
top H-5/6
TP3
RTC_WOT
MCU-port P0_40 which can have this signal multiplexed on its
output.
top I-5/6
TP4
WDG_OBSER
VE
MCU-port P0_43 which can have this signal multiplexed on its
output.
top F-10
TP7
HSF_SCK
High-Speed QSPI interface (with flash)
top K-5
TP8
HSF_SS
top L-5
TP9
HSF_SIO0
top K-5
TP10
HSF_SIO1
top K/L-5
TP11
HSF_SIO2
top L-5
TP12
HSF_SIO3
top L-5
TP13
GXF_SCK
Graphics-Controller QSPI interface (with flash)
top L/M-5
TP14
GXF_SS
top M/N-5
TP15
GXF_SIO0
top M-5
TP16
GXF_SIO1
top M-5
TP17
GXF_SIO2
top N-5
TP18
GXF_SIO3
top N-5
The crystal testpoints TP5 and 6 are very sensitive to noise and load-factors, especially capacitive
loads can change the frequency dramatically. If possible, the clocks should be measured indirectly
using a high-speed timer or SYSC_CKOT.
4.4 Status Display
For user information, there are four LEDs on the board. Each power-rail (the supply generated on-
board), is monitored by a single LED.
In addition, the reset-LED shows the status of the reset-line. For the default configuration and no
external reset (JTAG, button or from a plugged-under PCB), this is the status of the system-voltage
supervisor (SVS). It will be lit if any voltage-rail is out of its allowed limits.
Name
Color
Description (when lit)
Position
LD1
orange
5V0 rail up
top P-15
LD2
yellow
3V3 rail up
top O/P-15
LD3
green
1V2 rail up (driven by 3V3-rail)
top O-15
LD4
red
reset active
top O/P-14
