Fujitsu MB91150 Series, Hardware Manual, Page: 89 / 512

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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.11.4 Gear Control Register (GCR)
This register controls the gear function of the CPU and peripheral system clocks.
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Gear control register (GCR)
The register is configured as follows:
❍
[Bits 7 and 6]: CCK1 and CCK0
These bits specify the CPU system gear cycle. The relationship between these bits and the
cycle to be selected is shown below. These bits are initialized at reset.
❍
[Bit 5] DBLAK
This bit indicates a clock doubler operation status. This bit is read-only, and attempts to access
it for writing are ignored. The bit is initialized at reset.
A time lag occurs when switching the bus frequency. However, this bit allows checking whether
switching was actually performed.
GCR CCK1 CCK0 DBLAK DBLON PCK1 PCK0 - CHC 110011-1
000484 ( R/W ) (R/W ) ( R ) ( R/W ) (R/W) (R/W) ( - ) ( R/W)
Initial value
CCK1 CCK0 CHC
CPU machine clock (oscillation: input frequency
from X0)
0 0 0 PLL x 1
0 1 0 PLL x 1/2
1 0 0 PLL x 1/4
1 1 0 PLL x 1/8
0 0 1 Oscillation x 1/2
0 1 1 Oscillation x 1/2 x 1/2
1 0 1 Oscillation x 1/2 x 1/4
1 1 1 Oscillation x 1/2 x 1/8 [Initial value]
DBLAK Internal operating frequency: same as external operating frequency
0 Operating in 1:1 relationship [Initial value]
1 Operating in 2:1 relationship