Fujitsu MB91150 Series, Hardware Manual, Page: 423 / 512

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CHAPTER 20 CALENDAR MACROS
20.2 Calendar Macro Registers
The calendar macro registers include the following nine:
• Calendar block read/write control register (CAC)
• Second data register) (CA1)
• Minute data register) (CA2)
• Hour data register) (CA3)
• Day data register (CA4)
• Day-of-the-week data register (CA5)
• Month data register (CA6)
• Year data register (CA7)
• Calendar test register (CAS)
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Calendar block read/write control register (CAC)
The Calendar block read/write control register (CAC) has the following bit configuration:
[bit 7] RST
This bit initializes the calendar control circuit.
The calendar control circuit is initialized by writing 1.
CA1-7 and the counter are not initialized.
[bit 6 to 2] Reserved
This bit is a reserved bit that must be set to 0.
[bit1, 0] MD1 and MD0 mode setting bits
7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit
CAC RST - - - - - MD1 MD0
Initial value
00000000
B
[R/W]
MD1 MD0 Mode
0 0 Normal counter operation
0 1 Read mode
1 0 Write mode
1 1 Prohibited