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CHAPTER 17 DMA CONTROLLER
17.5 Transfer-Acceptance Signal Output and Transfer-End
Signal Output
Channels 0, 1 and 2 support a function for outputting the transfer-request-acceptance
signal from a pin.
When accepting transfer request input from a pin for DMA transfer, the DMAC outputs
the transfer-request-acceptance signal.
When accepting transfer request input from a pin for DMA transfer and ending the
transfer with the DMACT counter set to 0, the DMAC outputs the transfer-end signal.
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Transfer-acceptance signal output
The transfer-request-acceptance signal is output as active-low pulses when transfer data is
accessed. Using the AKSEn and AKDEn bits in DATCR, you can set whether to output that
signal synchronously with transfer source access, transfer destination access, or both of
transfer source access and transfer destination access.
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Transfer-end signal output
The transfer-end signal is output as active-low pulses when the final transfer data is accessed.
Using the EPSEn and EPDEn bits in DATCR, you can set whether to output that signal
synchronously with transfer source access, transfer destination access, or both of transfer
source access and transfer destination access.
Summary of Contents for MB91150 Series
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Page 3: ...FUJITSU LIMITED FR30 32 BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL ...
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Page 10: ...vi ...
Page 112: ...96 CHAPTER 3 MEMORY SPACE CPU AND CONTROL UNIT ...
Page 178: ...162 CHAPTER 5 I O PORTS ...
Page 214: ...198 CHAPTER 7 16 BIT RELOAD TIMER ...
Page 240: ...224 CHAPTER 8 PPG TIMER ...
Page 310: ...294 CHAPTER 13 8 10 BIT A D CONVERTER ...
Page 318: ...302 CHAPTER 14 8 BIT D A CONVERTER ...
Page 362: ...346 CHAPTER 15 UART ...
Page 420: ...404 CHAPTER 19 PERIPHERAL STOP CONTROL ...
Page 428: ...412 CHAPTER 20 CALENDAR MACROS ...
Page 503: ...487 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
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