Fujitsu MB90460 Series, Hardware Manual, Page: 97 / 739

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CHAPTER 5 CLOCK
5.1 Clock
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock. One internal clock cycle is regarded as one machine cycle.
Other clocks include a clock generated by source oscillation, called an oscillation clock,
and a clock generated by the internal PLL oscillation, called a PLL clock.
■
Clock
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external
clock to the clock generation block.
The clock generation block also contains the PLL clock multiplier circuit, which generates four clocks that
are multiples of the oscillation clock.
The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication
as well as controls internal clock operation by changing the clock with a clock selector.
●
Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
input of an external clock.
●
Main clock (MCLK)
The main clock, which is the oscillation clock divided by 2, supplies the clock input to the time-base timer
and the clock selector.
●
PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock with the internal PLL clock multiplier
circuit (PLL oscillation circuit). Selection can be made from among four different PLL clocks.
●
Machine clock (
φ
)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/
φ
). An operating machine clock can be selected from among the main clock that is
generated from the source clock frequency divided by 2 and the four clocks that are multiples of the source
clock frequency.
Note:
Although an oscillation clock of 3 MHz to 32 MHz can be generated when the operating voltage is
5 V, the maximum operating frequency for the CPU and peripheral functions is 16 MHz. If a
frequency multiplier rate exceeding the operating frequency is specified, devices will not operate
correctly.
If, for example, a source oscillation of 16 MHz is generated, only a multiplier of 1 can be specified.
A PLL oscillation of 3 to 16 MHz is possible, but this range depends on the operating voltage and
multiplier. See "Data Sheet", for details.