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CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.1
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■
A/D Control Status Register 1 (ADCS1)
Figure 20.4-2 A/D Control Status Register 1 (ADCS1)
PAU
S
(ADC
S
0)
S
T
S
1
S
TRT RE
S
V
S
T
S
0
INTE
0
1
Interr
u
pt re
qu
e
s
t en
ab
le
b
it
Di
sab
le
s
interr
u
pt re
qu
e
s
t o
u
tp
u
t
En
ab
le
s
interr
u
pt re
qu
e
s
t o
u
tp
u
t
BU
S
Y
INT
INTE
INT
Interr
u
pt re
qu
e
s
t fl
a
g
b
it
B
us
y
b
it
A/D conver
s
ion h
as
not
b
een completed
A/D conver
s
ion h
as
b
een completed
A/D convei
s
ion i
s
h
a
lted
A/D conver
s
ion i
s
in progre
ss
Cle
a
r
s
thi
s
b
it
No effect
S
top
s
the A/D conver
s
ion
No effect
0
1
Re
a
d
Write
Re
a
d
Write
BU
S
Y
0
1
S
TRT
A/D conver
s
ion
a
ctiv
a
tion
b
it
(
v
a
lid only when
a
ctiv
a
ted
b
y
s
oftw
a
re (ADC2: EXT= 0))
Re
s
erved
b
it
RE
S
V
Alw
a
y
s
write 0 to thi
s
b
it
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
S
T
S
1
S
T
S
0
A/D
a
ctiv
a
tion
s
elect
b
it
0
0
1
1
0
1
0
1
Activ
a
tion
b
y
s
oftw
a
re
Activ
a
tion
b
y extern
a
l trigger or
s
oftw
a
re
Activ
a
tion
b
y timer or
s
oftw
a
re
Activ
a
tion
b
y extern
a
l trigger, timer, or
s
oftw
a
re
Doe
s
not
a
ctiv
a
te the A/D conver
s
ion
Activ
a
te the A/D conver
s
ion f
u
nction
0
1
PAU
S
H
a
lt fl
a
g
b
it
(v
a
lid only when EI
2
O
S
i
s
us
ed)
A/D conver
s
ion i
s
not h
a
lted
A/D conver
s
ion i
s
h
a
lted
0
1
0000
3
5
H
00000000
B
R/W
W
-
: Re
a
d/write
: Write only
: Undefined
: Initi
a
l v
a
l
u
e
15
Addre
ss
Initi
a
l v
a
l
u
e
14
1
3
12
11
10
9
8
7
b
it
0
A/D conversion is halt.
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......