Fujitsu MB90460 Series, Hardware Manual, Page: 543 / 739

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CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.3 Request Level Setting Register (ELVR)
The request level setting register (ELVR) selects the level or edge of the signal input to
each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause.
■
Request Level Setting Register (ELVR)
Figure 18.4-4 Request Level Setting Register (ELVR)
Table 18.4-4 Function Eescription of Each bit of the Request Level Setting Register (ELVR)
Bit name Function
bit15
to
bit0
LB7, LB0 to LA7, LA0:
Request detection
selection bits
•
Each of these bits selects the level or edge of the signal input to the DTP/
external interrupt pin to be detected as a DTP/external interrupt cause.
•
Two bits are assigned to each pin.
(Reference)
If the selected detection signal is input to a DTP/external interrupt pin, the
external interrupt request flag bit is set to "1" regardless of the settings of the
DTP/interrupt enable register (ENIR).
Table 18.4-5 Correspondence between Request Level Setting Register (ELVR) and Each Channel
DTP/external interrupt pin Interrupt number Bit name
P63/INT7
#27 (1B
H
)
LB7, LA7
P16/INT6 LB6, LA6
P15/INT5
#25 (19
H
)
LB5, LA5
P14/INT4 LB4, LA4
P13/INT3
#22 (16
H
)
LB3, LA3
P12/INT2/DTTI1
*
LB2, LA2
P11/INT1
#20 (14
H
)
LB1, LA1
P10/INT0/DTTI0 LB0, LA0
*: Pin name not applicable to MB90465 series
LB 7 to
LB 0
LA 7 to
LA 0
Extern a l interr u pt re qu e s t detection s election b it s
0 0
L level i s to b e detected.
0
0
H level i s to b e detected.
1
1
Ri s ing edge i s to b e detected.
1
1
F a lling edge i s to b e detected.
Addre ss
0000 33
H
LB 3
7 0
LA 3 LB2 LA2 LB1 LA1 LB0 LA0
6 5 4 3 2 1
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
B
Initi a l v a l u e
LB7
15 b it 8
LA7 LB6 LA6 LB5 LA5 LB4 LA4
14 1 3 12 11 10 9
R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Re a d/write en ab led
:Initi a l v a l u e
00000000
B