Fujitsu MB90460 Series, Hardware Manual, Page: 540 / 739

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CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.1 DTP/interrupt Cause Register (EIRR)
The DTP/interrupt cause register (EIRR) stores and clears interrupt causes.
■
DTP/interrupt Cause Register (EIRR)
Figure 18.4-2 DTP/interrupt Cause Register (EIRR)
Notes:
• The value of the DTP/external interrupt request flag bit (EIRR:ER) is valid only when the
corresponding DTP/external interrupt request enable bit (ENIR:EN) is set to "1". When the DTP/
external interrupt is not enabled (ENIR:EN=0), the DTP/external interrupt cause bit may be set
regardless of the presence or absence of a DTP/external interrupt cause.
• Immediately before enabling the DTP/external interrupt (ENIR:EN=1), clear the corresponding
DTP/external interrupt request flag bit (EIRR:ER).
Addre ss
(ENIR)
R/W R/W R/W R/W
Initi a l v a l u e
0000 3 1
H
XXXXXXXX
B
ER7 ER6 ER5 ER4 ER 3 ER2 ER1 ER0
Extern a l interr u pt re qu e s t fl a g b it
No DTP/extern a l interr u pt i s inp u t
A DTP/extern a l interr u pt i s inp u t
Thi s b it i s cle a red
No effect
0
1
Re a d Write
ER7
ER0
R/W : Re a d/write
15 b it 14 1 3 12 11 10 9 8 7 0
R/W R/W R/W R/W
Table 18.4-1 Function Description of Each Bit of the DTP/interrupt Cause Register (EIRR)
Bit name Function
bit15
to
bit8
ER7 to ER0:
External interrupt
request flag bits
•
Each of these bits is set to "1" if a signal with the edge or level selected by bits LB7,
LA7 to LB0, LA0 of the request level setting register (ELVR) is input to the DTP/
external interrupt pin (stores an interrupt cause).
•
If these bits and corresponding bits EN7 to EN0 of the DTP/interrupt enable register
(ENIR) are "1", an interrupt request is output to the CPU.
•
Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit
value and has no effect on other bits.
(Note)
If more than one external interrupt request output is enabled (ENIR: EN7 to EN0 =
1), clear only the bit that caused the CPU to accept an interrupt (bits ER7 to ER0 set to
"1"). Do not clear the other bits without a reason.
(Reference)
When the extended intelligent I/O service (EI²OS) is activated, the corresponding
external interrupt request flag bit is automatically cleared when the transfer of one
data ends.