Fujitsu MB90460 Series, Hardware Manual, Page: 463 / 739

444
CHAPTER 16 PWC Timer
16.4.3 Division Rate Control Register (DIV0/DIV1)
The division rate control register (DIV0/DIV1) is used in the division period
measurement mode (PWCSL:MOD2, 1, and 0 = 011
B
). This register has no meaning in
other modes.
■
Division Rate Control Register (DIV0/DIV1)
Figure 16.4-5 Division Rate Control Register (DIV0/DIV1)
Address bit 7 6 5 4 3 2 1 0 Initial value
ch.0: 00000C
H
ch.1: 00002C
H
— — — — — —
DIV1 DIV0
------00
B
— — — — — — R/W R/W
DIV1 DIV0 Division rate selection bits
0 0
2
2
= divided by 4
0 1
2
4
= divided by 16
1 0
2
6
= divided by 64
1 1
2
8
= divided by 256
X : Indeterminate
R/W : Read and write
: Initial value
— : Not used
Table 16.4-3 Division Rate Control Register (DIV0/DIV1)
Bit name Function
bit7
to
bit2
Unused bit
•
The read value is indeterminate.
•
Writing to these bits has no effect on the operation.
bit1,
bit0
DIV1,DIV0:
Division rate selection bits
•
In the division range measurement mode, this register is used to divide the pulse input
from the measurement pin and measure the one-period width after division.
•
After reset, these bits are initialized to “00
B
”. These bits can be read and written.
(Note)
After the timer starts, the setting cannot be changed. Write these bits before the
timer has started or after the timer has stopped.