Fujitsu MB90460 Series, Hardware Manual, Page: 457 / 739

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CHAPTER 16 PWC Timer
16.4 PWC Timer Registers
Following are the PWC timer registers.
■
PWC Timer Registers
Figure 16.4-1 PWC Timer Registers
15 14 13 12 11 10 9 8
R/W
0
Address: ch.0 000009
H
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
STRT STOP EDIR EDIE OVIR OVIE ERR POUT
Reserved
Address: ch.0 000008
H
7 6 5 4 3 2 1 0
PWC control status register (Upper)
PWC control status register (Lower)
PWCSH0,
PWCSL0,
Initial value
Read/write
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
CKS1 CKS0 S/C MOD2 MOD1 MOD0
15 14 13 12 11 10 9 8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7 6 5 4 3 2 1 0
PWC data buffer register (Upper)
PWC data buffer register (Lower)
PWC0,PWC1
Initial value
Read/write
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Initial value
Read/write
7 6 5 4 3 2 1 0
R/W
0
R/W
0
— — — —
DIV1 DIV0
Division rate control register
Initial value
Read/write
ch.1 000029
H
ch.1 000028
H
Reserved
PWC0,PWC1
Address: ch.0 00000B
H
ch.1 00002B
H
Address: ch.0 00000A
H
ch.1 00002A
H
Address: ch.0 00000C
H
ch.1 00002C
H
— —
DIV0,DIV1
PW15 PW14 PW13 PW12 PW11 PW10 PW09 PW08
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
bit
bit
bit
bit
bit
PWCSH1
PWCSL1