Fujitsu MB90460 Series, Hardware Manual, Page: 448 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
15.7 Usage Notes on the Multi-pulse Generator
Notes on using the Multi-pulse Generator are given below.
■
Usage Notes on the Waveform Sequencer
●
Notes on using a program for setting
• Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from rising-
edge synchronization (IPCUR: WTS1,WTS0 = 01
B
) to falling-edge synchronization (IPCUR:
WTS1,WTS0 = 10
B
) or vice versa) is inhibited, no synchronization mode (IPCUR: WTS1,WTS0 = 00
B
)
must be the transit for such switch.
• When the data transfer method is changed, the next data buffer register to be selected is always specified
by the BNKF, RDA2 to RDA0 bits in the data output register (OPDR). This does not apply to the
OPDBR0 write method (OPCUR: OPS2 to OPS0 = 000
B
), in OPDBR0 write method BNKF, RDA2 to
RDA0 bits are ignored.
• Word access to output data register (OPDR) must be used.
• When using OPDBR0 write method for data transfer (OPCUR: OPS2 to OPS0 = 000
B
), word access to
output data buffer register 0 must be used, byte access to either lower register or upper register does not
start any transfer operation.
• In order to use the 16-bit reload timer underflow transfer method (OPCUR: OPS2 to OPS0 = 010
B
), the
reload timer should be used in "Reload Mode". Software trigger is needed to be used for the startup of
the reload timer. The 16-bit reload timer is needed for setting the update time in advance and executing
the continuous control action.
• In order to use the position detection and timer underflow transfer method (OPCUR: OPS2 to OPS0 =
011
B
or 111
B
), the reload timer should be used in "Single Shot Mode". TIN0O must be longer than two
machine cycles.
• Before DTTI1 circuit is in effect (OPCUR: DTIE = 1), make sure that the PORTx which is multiplexed
with the OPTx is configured as an output port by setting its data direction register (DDRx).
• Since the DTTI1 input control circuit uses a peripheral clock, input is invalidated even if the DTTI1
input is enabled (OPCUR: DTIE = 1) in a mode such as STOP mode in which the oscillator stops.
• In worst case the time from DTTI1 being recognized (after noise cancellation) to DTISP in effect takes
2 cycles, in best case it takes 1 cycle.
• Always change the D1 and D0 bits of noise cancellation control register (NCCR) when the noise
cancellation function is disabled (OPCUR: NRSL = 0).
• Always change the S21, S20, S11, S10, S01 and S00 bits of noise cancellation control register (NCCR)
when the noise cancellation function is disabled (IPCLR: SNC2 to SNC0 = 000
B
).