Fujitsu MB90460 Series, Hardware Manual, Page: 445 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
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16-bit Timer Timing
The 16-bit timer is incremented based on the prescaler clock and counts up at a rising edge.
Note:
Before the prescaler clock is changed, the Timer Counter should be disable first by setting the
TMEN bit to "0".
Figure 15.6-29 16-bit Timer Count Timing
The counter can be cleared upon a reset, software clear (TCLR), a match with Compare Clear Register, the
Write Timing signal or the Position Detection signal. By a reset, the counter is immediately cleared. By a
match with Compare Clear Register, software clear (TCLR), the Write Timing signal or the Position
Detection signal, the counter is cleared in synchronization with the count timing.
Figure 15.6-30 16-bit Timer Clear Timing
N
N+1
Counter value
Prescaler clock
N+2
N+3 N+4
CPU clock
N
N - 1
0000
H
Compare
register value
Compare match
Counter value
Prescaler clock
N
0001
H
0002
H
φ