Fujitsu MB90460 Series, Hardware Manual, Page: 409 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
15.4.7 Timer Control Status Register (TCSR)
The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit
timer.
■
Timer Control Status Register (TCSR)
Figure 15.4-12 Timer Control Status Register (TCSR)
Addre ss b it 7 6 5 4 3 2 1 0 Initi a l v a l u e
0000 8 E
H
TCLR
MODE ICLR ICRE TMEN CLK2 CLK1 CLK0 00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
CLK2 CLK1 CLK0
Clock frequency s election bit
Count
clock
φ
= 16 MHz
φ
= 8 MHz
φ
= 4 MHz
φ
= 1 MHz
0 0 0
φ
62.5 n s 125 n s 0.25
µ
s 1
µ
s
0 0 1
φ
/2
125 n s 0.25
µ
s 0.5
µ
s 2
µ
s
0 1 0
φ
/4 0.25
µ
s 0.5
µ
s 1
µ
s 4
µ
s
0 1 1
φ
/ 8 0.5
µ
s 1
µ
s 2
µ
s 8
µ
s
1 0 0
φ
/16
1
µ
s 2
µ
s 4
µ
s 16
µ
s
1 0 1
φ
/ 3 2
2
µ
s 4
µ
s 8
µ
s 3 2
µ
s
1 1 0
φ
/64
4
µ
s 8
µ
s 16
µ
s 64
µ
s
1 1 1
φ
/12 8
8
µ
s 16
µ
s 3 2
µ
s 12 8
µ
s
φ
: M a chine cycle
TMEN Timer enable bit
0 Co u nting i s di sab led. (Initi a l v a l u e)
1 Co u nting i s en ab led.
ICRE Compare clear interrupt reque s t enable bit
0 Interr u pt i s di sab led.
1 Interr u pt i s en ab led.
ICLR
Compare clear interrupt reque s t fla g bit
Read Write
0 No interr u pt re qu e s t. Cle a r thi s b it.
1 H as interr u pt re qu e s t. No effect.
MODE Counter re s et condition bit
0 Re s et co u nter b y write timing trigger.
1 Re s et co u nter b y po s ition detection trigger.
TCLR
Timer clear bit
Read Write
0
Alw a y s re a d as “0”.
No effect.
1
Initi a lize co u nter to “0000
H
”.
X : Indetermin a te
R/W : Re a d ab le a nd writ ab le
: Initi a l v a l u e
— : Not us ed