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372
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.1
Output Control Register (OPCR)
The Output Control Register (OPCR) is a register which enables the write timing
interrupt and flag, position detect interrupt and flag, sets the data transfer method, and
sets the control of the OPT5 to OPT0 and DTTI1 pins.
■
Output Control Upper Register (OPCUR)
Figure 15.4-2 Output Control Upper Register (OPCUR)
Addre
ss
b
it
15
14
1
3
12
11
10
9
8
Initi
a
l v
a
l
u
e
0000
8
B
H
DTIE
DTIF
NR
S
L
OP
S
2
OP
S
1
OP
S
0
WTIF
WTIE
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTIE
Write timin
g
interrupt enable bit
0
Di
sab
le interr
u
pt.
1
En
ab
le interr
u
pt.
WTIF
Write timin
g
interrupt reque
s
t fla
g
bit
Read
Write
0
No v
a
lid detected.
Cle
a
r thi
s
b
it.
1
V
a
lid detected.
No effect.
OP
S
2
OP
S
1
OP
S
0
Function
0
0
0
D
a
t
a
tr
a
n
s
fer from OPDBR0 to OPDR
a
fter
OPDBR0 i
s
written
b
y
s
oftw
a
re.
0
0
1
D
a
t
a
tr
a
n
s
fer from OPDBR to OPDR i
s
triggered
b
y the16-
b
it relo
a
d timer 0
u
nderflow.
0
1
0
D
a
t
a
tr
a
n
s
fer from OPDBR to OPDR i
s
triggered
b
y the po
s
ition detection inp
u
t.
0
1
1
D
a
t
a
tr
a
n
s
fer from OPDBR to OPDR i
s
triggered
b
y the write
s
ign
a
l gener
a
ted
b
y the 16-
b
it relo
a
d
timer 0
u
nderflow, the 16-
b
it timer i
s
s
t
a
rted
b
y
the po
s
iton detection comp
a
ri
s
on circ
u
it.
1
0
0
D
a
t
a
tr
a
n
s
fer from OPDBR to OPDR i
s
triggered
b
y the write
s
ign
a
l gener
a
ted either
b
y the 16-
b
it
relo
a
d timer 0
u
nderflow, or
b
y the po
s
ition
detection inp
u
t.
1
0
1
One-
s
hot po
s
ition dectection or timer
u
nderflow.
1
1
0
One-
s
hot po
s
ition dectection.
1
1
1
One-
s
hot po
s
ition dectection
a
nd timer
u
nderfow.
NR
S
L
Noi
s
e filter enable bit
0
DTTI1 inp
u
t doe
s
not go thro
u
gh the noi
s
e filter.
1
DTTI1 inp
u
t goe
s
thro
u
gh the noi
s
e filter.
DTIF
DTTI1 interrupt reque
s
t fla
g
bit
Read
Write
0
No v
a
lid detected.
Cle
a
r thi
s
b
it.
1
V
a
lid detected.
No effect.
DTIE
DTTI1 control enable bit
0
Di
sab
le control
b
y the DTTI1 inp
u
t.
1
En
ab
le control
b
y the DTTI1 inp
u
t.
X :
Indetermin
a
te
R/W : Re
a
d
ab
le
a
nd writ
ab
le
: Initi
a
l v
a
l
u
e
—
: Not
us
ed
Summary of Contents for MB90460 Series
Page 1: ...The following document contains information on Cypress products ...
Page 3: ......
Page 5: ......
Page 9: ...iv ...
Page 41: ...22 CHAPTER 1 OVERVIEW ...
Page 45: ...26 CHAPTER 2 NOTES ON HANDLING DEVICES ...
Page 83: ...64 CHAPTER 3 CPU ...
Page 95: ...76 CHAPTER 4 RESET ...
Page 107: ...88 CHAPTER 5 CLOCK ...
Page 131: ...112 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 175: ...156 CHAPTER 7 INTERRUPT ...
Page 181: ...162 CHAPTER 8 MODE SETTING ...
Page 223: ...204 CHAPTER 9 I O PORT ...
Page 237: ...218 CHAPTER 10 TIME BASE TIMER ...
Page 247: ...228 CHAPTER 11 WATCHDOG TIMER ...
Page 275: ...256 CHAPTER 12 16 BIT RELOAD TIMER ...
Page 373: ...354 CHAPTER 14 MULTI FUNCTIONAL TIMER ...
Page 485: ...466 CHAPTER 16 PWC Timer ...
Page 531: ...512 CHAPTER 17 UART ...
Page 559: ...540 CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ...
Page 589: ...570 CHAPTER 20 8 10 BIT A D CONVERTER ...
Page 601: ...582 CHAPTER 21 ROM CORRECTION FUNCTION ...
Page 633: ...614 CHAPTER 23 512K 1024K BIT FLASH MEMORY ...
Page 645: ...626 CHAPTER 24 EXAMPLE OF F2 MC 16LX MB90F462 F462A F463A CONNECTION FOR SERIAL WRITING ...
Page 715: ...696 APPENDIX ...
Page 716: ...697 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 739: ......