Fujitsu MB90460 Series, Hardware Manual, Page: 369 / 739

350
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■
Usage Notes on the 16-bit Input Capture
●
Notes about interrupts
• When the ICP bit of the input capture control status register (PICSL01/ICSL23) is set to "1" and an
interrupt request is enabled (PICSL01/ICSL23:ICE=1), control cannot be returned from interrupt
processing. Always clear the ICP bit.
• If input capture pins IN is toggled after ICP bit is set but before interrupt routine is processed, the edge
indication bit (ICSH23:IEI3,IEI2 or PICSH01:IEI1,IEI0) will show the latest edge detected.
• Since the 16-bit input capture shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI
2
OS is used by the 16-bit input capture, shared resource interrupts must be disabled.
■
Usage Notes on the Waveform Generator
●
Notes on using a program for setting
• Change the TMD2, TMD1 and TMD0 bits of the 16-bit timer control register (DTCR0/DTCR1/
DTCR2) when the waveform generator is under operation (TMD2 to TMD0=001
B
, 010
B
, 100
B
or
111
B
), always be sure no trigger source and timer is not counting. Otherwise unexpected waveform in
RTO will be occurred due to prescheduled output by previous trigger. But RTO output becomes normal
once after timer is underflow or retriggered by new trigger source in new mode setting.
Trigger source is H level of RT when TMD2 to TMD0=001
B
, rising edge of RT when TMD2 to
TMD0=010
B
, rising/falling edge of RT when TMD2 to TMD0=100
B
or rising/falling edge of PPG0
when TMD2 to TMD0=111
B
.
For example, changing TMD2 to TMD0 from 100
B
to 111
B
, you can set in following procedures
1) set TMRR0/TMRR1/TMRR2 to a very small value like 0001
H
2) set RT1/RT3/RT5 to output "L"/"H" and wait until timer 0/1/2 underflow
3) change mode bits TMD2, TMD1 and TMD0 and corresponding setting
4) corrected output waveform will appear in RTO pins one machine cycle later
• Writing a value in 16-bit timer register (TMRR0/TMRR1/TMRR2) during timer counting, new value
will be valid at the next timer trigger. And always be sure to use a word transfer instruction (MOVW A,
dir, etc.) to access timer register.
• Change the DCK2, DCK1 and DCK0 bits of the waveform control register (SIGCR) when the timer is
not counting.
• Change the NWS1 and NWS0 bits of waveform control register (SIGCR) when the noise cancellation
function is disabled (SIGCR: NRSL=0).
●
Notes about interrupts
• When the TMIF bit of the timer control register (DTCR) is set to "1" and an interrupt request is enabled
(DTCR:TMIE=1), control cannot be returned from interrupt processing. Always clear the TMIF bit.
• When the DTIF bit of the waveform control register (SIGCR) is set to "1", control cannot be returned
from interrupt processing. Always clear the DTIF bit.
• Since the waveform generator shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI
2
OS is used by the waveform generator, shared resource interrupts must be disabled.