Fujitsu MB90460 Series, Hardware Manual, Page: 332 / 739

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CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.8 16-bit Timer Register (TMRR0/TMRR1/TMRR2)
16-bit timer registers hold the compare value of 16-bit timers.
■
16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
Figure 14.4-19 16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
These registers are used to store the comparison value of 16-bit timers. The value in these registers will be
reloaded when the 16-bit timer is started to operate. Therefore, if the value is re-written into these registers
during timer operation, these value will be valid at the next timer initiation/operation.
In dead-time timer mode, these registers are used to set the non-overlap time.
• Non-overlap time = (set value + 1)
×
selected clock.
Notes:
• The value of "0000
H
" cannot be set.
• The maximum offset of non-overlap time is -1 selected clock.
In timer mode, these registers are used to set the GATE time for PPG timer 0 operation.
• GATE time = (set value + 1)
×
selected clock.
Notes:
• The value of "0000
H
" cannot be set and maximum offset is -1 selected clock.
• The maximum offset of GATE time is -1 selected clock.
16-bit Timer Register (Lower)
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Initial value
Read/write
TMRR0/TMRR1/
Address: ch.0 000050
H
ch.1 000052
H
ch.2 000054
H
7 6 5 4 3 2 1 0
16-bit Timer Register (Upper)
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Initial value
Read/write
TMRR0/TMRR1/
Address: ch.0 000051
H
ch.1 000053
H
ch.2 000055
H
15 14 13 12 11 10 9 8
TR15 TR14 TR13 TR12 TR11 TR10 TR09 TR08
TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00
bit
bit
TMRR2
TMRR2