Fujitsu MB90460 Series, Hardware Manual, Page: 314 / 739

295
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.3 Timer Control Status Register (TCCSH, TCCSL)
The timer control status register (TCCS) is a 16-bit register and used to control the
operation of 16-bit free-run timer.
■
Timer Control Status Register, Upper Byte (TCCSH)
Figure 14.4-8 Timer Control Status Register (TCCSH)
Addre ss bit15 14 1 3 12 11 10 9 8 Initial value
00005F
H
ECKE IRQZF IRQZE M S I2 M S I1 M S I0 ICLR ICRE 00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
ICRE Compare clear interrupt reque s t enable bit
0 Di sab le interr u pt re qu e s t
1 En ab le interr u pt re qu e s t
ICLR
Compare clear interrupt fla g bit
Read Write
0 No comp a re-cle a r m a tch Cle a r thi s b it
1 Comp a re-cle a r m a tch No effect
M S I2 M S I1 M S I0 Interrupt ma s kin g s election bit s
0 0 0 Interr u pt i s gener a ted when 1 s t m a tch
0 0 1 Interr u pt i s gener a ted when 2nd m a tch
0 1 0 Interr u pt i s gener a ted when 3 rd m a tch
0 1 1 Interr u pt i s gener a ted when 4th m a tch
1 0 0 Interr u pt i s gener a ted when 5th m a tch
1 0 1 Interr u pt i s gener a ted when 6th m a tch
1 1 0 Interr u pt i s gener a ted when 7th m a tch
1 1 1 Interr u pt i s gener a ted when 8 th m a tch
IRQZE Zero detect interrupt reque s t enable bit
0 Di sab le interr u pt re qu e s t
1 En ab le interr u pt re qu e s t
IRQZF
Zero detect interrupt fla g bit
Read Write
0 No zero detect Cle a r thi s b it
1 Zero detect No effect
ECKE Clock s election bit
0 Intern a l clock
1 Extern a l clock
R/W : Re a d a nd Write
: Initi a l v a l u e