Fujitsu MB90460 Series, Hardware Manual, Page: 285 / 739

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CHAPTER 13 16-BIT PPG TIMER
13.4.3 PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
PPG duty setting buffer register is used to control the duty ratio of the output pulses
generated by PPG.
■
PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
Figure 13.4-4 PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
These are 16-bit registers that are used to control the duty ratio of the output pulses generated by PPG. The
initial value of them are undetermined, so that these registers must be set a value before starting an
operation. Word access instruction to these registers are recommended. These registers are write-only.
Data transfer from duty setting buffer register to duty setting register is at counter borrow or trigger or
retrigger if enabled.
Setting the same value in both the period setting register and duty setting register outputs all "H"s for
normal polarity and all "L"s for inverted polarity.
The output of the PPG is indeterminate if PCSR < PDUT.
Note:
Duty setting buffer register can be written in the case of not updating period setting buffer register.
15 14 13 12 11 10 9 8
PPG Duty Setting Buffer Register (Upper)
7 6 5 4 3 2 1 0
PPG Duty Setting Buffer Register (Lower)
Address: ch.0 00003D
H
ch.1 000045
H
ch.3 00004D
H
PDUT0 to
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Initial value
Read/write
Address: ch.0 00003C
H
ch.1 000044
H
ch.3 00004C
H
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
Initial value
Read/write
PDUT0 to
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
bit
bit
PDUT2
PDUT2