Fujitsu MB90460 Series, Hardware Manual, Page: 258 / 739

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CHAPTER 12 16-BIT RELOAD TIMER
12.4.2 Timer Control Status Register, Lower Byte (TMCSRL0/
TMCSRL1)
The lower seven bits of the timer control status registers (TMCSR0/TMCSR1) are used
to set operating conditions for the 16-bit reload timer, enable and disable operation,
control interrupts, and check the status.
■
Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
Figure 12.4-3 Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
Addre ss
TMC S RL0
0000 8 2
H
TMC S RL1
0000 8 6
H
Initi a l v a l u e
00000000
B
MOD0* OUTE OUTL RELD INTE UF CNTE TRG (TMC S R:H)
15 b it
R/W R/W R/W R/W R/W R/W R/W R/W
8 6 7 5 4 3 2 1 0
TRG
0
No effect
After relo a ding, co u nting s t a rt s . 1
S oftw a re trigger b it
INTE
0
Di sab le u nderflow interr u pt
En ab le u nderflow interr u pt
1
Underflow interr u pt en ab le b it
RELD
0
S ingle- s hot mode
Relo a d mode 1
Relo a d s election b it
CNTE
0
Co u nting s topped
Co u nting en ab led (w a it for the s t a rt trigger) 1
Co u nt en ab le b it
UF
D u ring re a ding
D u ring writing
Underflow interr u pt re qu e s t fl a g b it
0 Witho u t co u nter u nderflow
With co u nter u nderflow
Thi s b it i s cle a red.
No effect
1
OUTL
In s ingle- s hot mode (RELD = 0) In relo a d mode (RELD = 1)
Pin o u tp u t level s election b it
0
Squa re w a ve of H d u ring co u nting
Squa re w a ve of L d u ring co u nting
Toggle o u tp u t of L when co u nting i s s t a rted.
Toggle o u tp u t of H when co u nting i s s t a rted.
1
OUTE
Pin f u nction s
Regi s ter s a nd pin s corre s ponding to e a ch ch a nnel
TMC S R0
P16
TO0
P21
TO1
TMC S R1
Timer o u tp u t en ab le b it
0
Gener a l-p u rpo s e port
Timer o u tp u t
1
R/W: Re a d/write
: Initi a l v a l u e
* : S ee S ection 12.4.1, "Timer control s t a t us regi s ter, u pper b yte", for MOD0 ( b it 7)
D u ring writing
D u ring re a ding
Alw a y s re a d "0"