Fujitsu MB90460 Series, Hardware Manual, Page: 256 / 739

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CHAPTER 12 16-BIT RELOAD TIMER
12.4.1 Timer Control Status Register, Upper Byte (TMCSRH0/
TMCSRH1)
High-order bit11 to bit8 and low-order bit7 of the timer control status registers
(TMCSR0/TMCSR1) are used to select the operating mode of the 16-bit reload timer and
set the operating conditions. This section describes low-order bit7: the MOD0 bit.
■
Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
Figure 12.4-2 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
C S L1
MOD1 C S L0
R/W R/W R/W R/W R/W
MOD2 MOD1 MOD0
0
0
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
MOD2 MOD1 MOD0
X
X
X
X
0
0
1
1
0
1
0
1
(TMC S R:L)
TMC S RH0
0000 83
H
TMC S RH1
0000 8 7
H
C S L1 C S L0
0
0
1
1
0
1
0
1
----00000
B
R/W
X
Addre ss
Initi a l v a l u e
Re a d/Write
Initi a l v a l u e
Undefined
Not us ed
M a chine cycle. V a l u e in p a renthere s ( ) indic a te s the v a l u e when m a chine clock i s 16MHz
Oper a ting mode s election b it
Inp u t pin f u nction
V a lid edge a nd level
Trigger di sab led
Trigger inp u t
G a te inp u t
(Intern a l clock mode)
Ri s ing edge
F a lling edge
Both edge s
"L" level
"H" level
Oper a ting mode s election b it
(Event co u nt mode)
Inp u t pin f u nction
V a lid edge
Ri s ing edge
F a lling edge
Both edge s
Trigger inp u t
Co u nt clock s election b it
F u nction Co u nt clock
1
5
3
Intern a l clock mode
Event co u nt mode
Extern a l event inp u t
MOD2 MOD0
2
2
2
(0.125 s )
(0.5 s )
(2.0 s )
b it 15 14 1 3 12 11 10 9 8 7 6 0