Fujitsu MB90460 Series, Hardware Manual, Page: 244 / 739

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CHAPTER 11 WATCHDOG TIMER
Figure 11.4-2 Clear Timing and Watchdog Timer Intervals
[WDG timer block diagram]
2-bit counter
Clock
WTE bit
Count enable
Divide-by-
Reset
Reset signal
selector
two circuit circuit
Count enabling and clearing
output circuit
Divide-by-
two circuit
[Minimum interval] When the WTE bit is cleared immediately before the count clock rises:
Count start
Counter clearing
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
7 x (count clock cycle/2)
WTE bit clearing Watchdog reset generation
Reset signal d
9 x (count clock cycle/2)
Reset signal d
WTE bit clearing Watchdog reset generation
[Maximum interval] When the WTE bit is cleared immediately after the count clock rises:
Count start
Counter clearing
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling