Fujitsu MB90460 Series, Hardware Manual, Page: 103 / 739

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CHAPTER 5 CLOCK
5.4 Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■
Main Clock Mode and PLL Clock Mode
●
Main clock mode
In main clock mode, the main clock, whose frequency is the oscillation clock divided by 2, is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
●
PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0).
■
Clock Mode Transition
Switching between main clock mode and PLL clock mode is done by writing to the MCS bit of the clock
selection register (CKSCR).
●
Switching from main clock mode to PLL clock mode
When the MCS bit of CKSCR is "1" and "0" is written to it, the switch from the main clock to a PLL clock
occurs after the PLL clock oscillation stabilization wait period (2
14
/HCLK).
●
Switching from PLL clock mode to main clock mode
When the MCS bit of CKSCR is "0" and "1" is written to it, the switch from the PLL clock to the main
clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 8 PLL clocks).
Note:
Even though the MCS bit of CKSCR is rewritten, machine clock switching does not occur
immediately. When operating a resource that depends on the machine clock, make sure that
machine clock switching has been done by referring to the MCM bit of CKSCR before operating the
resource. If the mode is switched to another clock mode or low-power-consumption mode before
completion of switching, the mode may not be switched.
■
Selection of a PLL Clock Multiplier
Writing a value from “00
B
” to “11
B
” to the CS1 and CS0 bits of CKSCR selects one to the four PLL clock
multipliers.
■
Selection of a PLL Clock Multiplier
Writing a value from “00
B
” to “11
B
” to the CS1 and CS0 bits of CKSCR selects one to the four PLL clock
multipliers.
■
Machine Clock
The machine clock may be either a PLL clock output from the PLL multiplier circuit or the clock that is the
source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions.
Either the main clock or a PLL clock can be selected by writing to the MCS bit of CKSCR.