Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 23 CAN CONTROLLER
23.6.5 Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
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Bit Timing Register (BTR)
Figure 23.6-6 Configuration of the Bit Timing Register (BTR)
Note:
This register should be set during bus operation stop (HALT = 1).
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Bit Timing Register (BTR) Contents
15 bit
bit
14 13 12 11 10 9 8
Initial value
X 1 1 1 1 1 1 1
B
Address:
H
CAN0: 003707
CAN1: 003907
CAN2: 003B07
CAN3: 003D07
CAN4: 003F07
H
H
H
H
BTR (upper)
Initial value
1 1 1 1 1 1 1 1
B
Address:
H
CAN0: 003706
CAN1: 003906
CAN2: 003B06
CAN3: 003D06
CAN4: 003F06
H
H
H
H
BTR (lo w er)
- TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0
- R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
R/W : Readable and w ritable
Table 23.6-6 Function of Each Bit of the Bit Timing Register (BTR)
Bit name Function
bit15 Undefined
bit14 to
bit12
TS2.2 to TS2.0:
Time segment2
setting bits These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2).
The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN
specification.
bit11 to
bit8
TS1.3 to TS1.0:
Time segment1
setting bits These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1).
The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specification.
bit7, bit6
RSJ1, RSJ0:
Resynchronization
jump width setting
bits These bits define the number of the time quanta (TQ’s) for the resynchronization jump
width.
bit5 to bit0
PSC5 to PSC0:
Prescaler setting
bits These bits define the time quanta (TQ) of the CAN controller. (see below for details.)