Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 23 CAN CONTROLLER
23.6.4 Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
■
Receive and Transmit Error Counters (RTEC)
Figure 23.6-5 Configuration of the Receive and Transmit Error Counters
■
Receive and Transmit Error Counters (RTEC) Contents
15 b it
b it
14 1 3 12 11 10 9 8
Initi a l v a l u e
0 0 0 0 0 0 0 0
B
R R R R R R R R
Addre ss :
H
CAN0: 00 3 705
CAN1: 00 3 905
CAN2: 00 3 B05
CAN 3 : 00 3 D05
CAN4: 00 3 F05
H
H
H
H
RTEC ( u pper)
Initi a l v a l u e
0 0 0 0 0 0 0 0
B
Addre ss :
H
CAN0: 00 3 704
CAN1: 00 3 904
CAN2: 00 3 B04
CAN 3 : 00 3 D04
CAN4: 00 3 F04
H
H
H
H
RTEC (lower)
R R R R R R R R
TEC7 TEC6 TEC5 TEC4 TEC 3 TEC2 TEC1 TEC0
REC7 REC6 REC5 REC4 REC 3 REC2 REC1 REC0
7 6 5 4 3 2 1 0
Table 23.6-5 Function of Each Bit of the Receive and Transmit Error Counters (RTEC)
Bit name Function
bit15 to
bit8
TEC7 to TEC0:
Transmit error
counter bits
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Bus Off is indicated
for the node status (NS1 and NS0 of control status register CSR = 11
B
).
bit7 to bit0
REC7 to REC0:
Receive error
counter bits
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Error Passive is
indicated for the node status (NS1 and NS0 of control status register CSR = 10
B
).