288
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.2
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■
Upper Bits of the A/D Control Status Register 1 (ADCS1)
Figure 18.4-4 Configuration of the A/D Control Status Register 1 (ADCS1)
PAU
S
(ADC
S
0)
S
T
S
1
S
TRT
Re
s
erved
Re
s
erved
S
T
S
0
INTE
0
1
Interr
u
pt re
qu
e
s
t en
ab
le
b
it
Di
sab
le
s
interr
u
pt re
qu
e
s
t o
u
tp
u
t.
En
ab
le
s
interr
u
pt re
qu
e
s
t o
u
tp
u
t.
BU
S
Y
INT
INTE
INT
Interr
u
pt re
qu
e
s
t fl
a
g
b
it
B
us
y
b
it
A/D conver
s
ion h
as
not
b
een completed.
A/D conver
s
ion h
as
b
een completed.
A/D conver
s
ion i
s
h
a
lted.
A/D conver
s
ion i
s
in progre
ss
.
Cle
a
r
s
thi
s
b
it.
No ch
a
nge, no effect on other
b
it
s
.
S
top
s
the A/D conver
s
ion.
No ch
a
nge, no effect on other
b
it
s
.
0
1
Re
a
ding
Writing
Re
a
ding
Writing
BU
S
Y
0
1
S
TRT
A/D conver
s
ion
a
ctiv
a
tion
b
it
(
v
a
lid only when
a
ctiv
a
ted
b
y
s
oftw
a
re (ADC2: EXT= 0))
Re
s
erved
b
it
Alw
a
y
s
write "0" to thi
s
b
it.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
S
T
S
1
S
T
S
0
A/D
a
ctiv
a
tion
s
elect
b
it
0
0
1
1
0
1
0
1
Activ
a
tion
b
y
s
oftw
a
re.
Activ
a
tion
b
y extern
a
l trigger or
s
oftw
a
re.
Activ
a
tion
b
y 16-
b
it relo
a
d timer 1 o
u
tp
u
t
or
s
oftw
a
re.
Activ
a
tion
b
y extern
a
l trigger, 16-
b
it
relo
a
d timer 1 o
u
tp
u
t, or
s
oftw
a
re.
Doe
s
not
a
ctiv
a
te the A/D conver
s
ion.
Activ
a
te the A/D conver
s
ion f
u
nction.
0
1
PAU
S
H
a
lt fl
a
g
b
it
(v
a
lid only when EI
2
O
S
i
s
us
ed)
A/D conver
s
ion i
s
not h
a
lted.
A/D conver
s
ion i
s
h
a
lted.
0
1
0000
3
5
H
00000000
B
R/W
W
-
: Re
a
d
ab
le
a
nd writ
ab
le
: Write only
: Undefined
: Initi
a
l v
a
l
u
e
15
b
it
Addre
ss
Initi
a
l v
a
l
u
e
14
1
3
12
11
10
9
8
7
0
Summary of Contents for MB90390 Series
Page 2: ......
Page 4: ......
Page 17: ...xiii APPENDIX D List of Interrupt Vectors 690 INDEX 695 ...
Page 18: ...xiv ...
Page 132: ...104 CHAPTER 5 CLOCKS ...
Page 152: ...124 CHAPTER 6 CLOCK MODULATOR ...
Page 210: ...182 CHAPTER 11 TIME BASE TIMER ...
Page 218: ...190 CHAPTER 12 WATCHDOG TIMER ...
Page 264: ...236 CHAPTER 14 16 BIT RELOAD TIMER WITH EVENT COUNT FUNCTION ...
Page 274: ...246 CHAPTER 15 WATCH TIMER ...
Page 306: ...278 CHAPTER 17 DTP EXTERNAL INTERRUPTS ...
Page 338: ...310 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 364: ...336 CHAPTER 19 UART0 UART1 ...
Page 398: ...370 CHAPTER 20 UART2 UART3 Figure 20 5 2 ORE Set Timing Receive data RDRF ORE ...
Page 432: ...404 CHAPTER 20 UART2 UART3 ...
Page 482: ...454 CHAPTER 22 SERIAL I O ...
Page 560: ...532 CHAPTER 24 STEPPING MOTOR CONTROLLER ...
Page 582: ...554 CHAPTER 27 ROM MIRRORING MODULE ...
Page 632: ...604 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ...
Page 722: ...694 APPENDIX ...
Page 723: ...695 INDEX The index follows on the next page This is listed in alphabetic order ...
Page 740: ......