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130nm node CMOS Process (CS90A)

Technology Roadmap

Features

Technology Code

CS90A

Transistor

UHS

HS

ST

LL

Physical Gate Length (nm)

110

110

110

110

Gate Oxide Thickness (nm)

2.9

2.9

2.9

2.9

Supply Voltage (V)

1.2

1.2

1.2

1.2

NMOS Ids (µA/µm)

780

678

570

390

PMOS Ids (µA/µm)

-321

-276

-218

-150

NMOS Ioff (nA/µm)

36

4

0.18

0.005

PMOS Ioff (nA/µm)

-18

-3.1

-0.22

-0.015

Gate Leak Current (nA/µm)

0.01

0.01

0.01

0.01

Basic Gate Delay (ps)

14

17

28

45

Number of Available Poly Layer

1

Number of Available Metal Layer

8Cu+1Al

Via Filling

Cu Dual Damascene

ILD Structure

Hybrid Low-k

SRAM Cell Size (µm2)

1.98

Dual Gate Oxide Options

Available

Mixed Signal Options

Available

RF Elements

MIM cap., Poly Resistor, Inductor

Fuse

RAM Redundancy

180-nm

Cu

130-nm

Cu+Low+k   

90-nm 

Cu+VLK   

65-nm

45-nm

32-nm

CS80/80A

1000

500

200

100

50

20

10

1998

2000

G: Generic, LL: Low Leakage

2002

2004

2006

2008

2010

2012

CS90A

CS100A_LL

For ASIC & COT

Year (Production Start)

Physical Gate Length (nm)

For COT

CS200A_LL

CS200A_G

CS200

CS100

CS90

CS100A_G

Mie plant

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