MB95630H Series
MN702-00009-2v0-E
FUJITSU SEMICONDUCTOR LIMITED
445
CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
21.6.6
16-bit MPG Compare Clear Register (Upper/Lower)
(CPCUR/CPCLR)
The 16-bit MPG compare clear register (upper/lower) (CPCUR/CPCLR) consists
of two 8-bit registers. CPCUR is the upper byte register and CPCLR the lower
byte register. When the values of these registers match the count value of the
16-bit timer, the 16-bit timer is reset to "0x0000".
The 16-bit MPG compare clear register (upper) (CPCUR) and the 16-bit MPG compare clear
register (lower) (CPCLR) are two 8-bit registers used to compare with the counter value of the
16-bit timer. Since the initial values of these registers are indeterminate, write values to these
registers before starting an operation.
Always use one of the following methods to access these registers.
•
Use the "MOVW" instruction (use a 16-bit access instruction to read and write the CPCUR
register address).
•
Use the "MOV" instruction to read or write CPCUR first and then CPCLR.
■
Register Configuration
Notes:
When the values of these registers match the count value of the 16-bit timer, the 16-bit
timer is reset to "0x0000" and the compare clear interrupt request flag bit (TCSR:ICLR) is
set. In addition, when the interrupt operation is enabled, an interrupt request is sent to the
CPU.
If the values loaded to the 16-bit MPG compare clear register (upper) (CPCUR) and the
16-bit MPG compare clear register (lower) (CPCLR) are the same as the 16-bit timer
counter value, the compare operation will not be performed until the next occasion in
which the values of CPCUR and CPCLR are the same as the 16-bit timer counter value.
CPCUR
bit
7
6
5
4
3
2
1
0
Field
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
CPCLR
bit
7
6
5
4
3
2
1
0
Field
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
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