MB95630H Series
18
FUJITSU SEMICONDUCTOR LIMITED
MN702-00009-2v0-E
CHAPTER 3 CLOCK CONTROLLER
3.1 Overview
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Configuration of Clock Controller
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Main clock oscillator circuit
This block is the oscillator circuit for the main clock.
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Subclock oscillator circuit
This block is the oscillator circuit for the subclock.
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Main CR clock oscillator circuit
This block is the oscillator circuit for the main CR clock.
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Main CR PLL clock oscillator circuit
This block is the oscillator circuit for the main CR PLL clock.
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Sub-CR clock oscillator circuit
This block is the oscillator circuit for the sub-CR clock.
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System clock selector
This block selects a clock according to the clock mode used from the following five types of
source clock: main clock, subclock, main CR clock, main CR PLL clock and sub-CR clock.
The source clock selected is divided by the prescaler. The divided clock is called "machine
clock", which is to be supplied to the clock control circuit.
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Clock control circuit
This block controls the supply of the machine clock to the CPU and each peripheral function
according to the standby mode used or oscillation stabilization wait time.
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Oscillation stabilization wait circuit
This block outputs oscillation stabilization wait time signals according to clocks that are
enabled to operate.
In the case of main clock, its oscillation stabilization signal can be selected from 14 types of
oscillation stabilization signals created by a dedicated timer in the oscillation stabilization wait
circuit. In case of subclock, its oscillation stabilization signal can be selected from 15 types of
oscillation stabilization signals created by the same dedicated timer.
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System clock control register (SYCC)
This register selects a clock mode and a machine clock divide ratio, and indicates the current
clock mode.
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PLL control register (PLLC)
This register controls the main CR PLL clock multiplication rate settings.
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Standby control register (STBC)
This register controls the transition from RUN state to standby mode, the setting of pin states in
stop mode, time-base timer mode, or watch mode, and the generation of software resets.
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