Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
33
Copyright © 2015 Future Technology Devices International Limited
2.3.11
SPI_MASTER_TRANSFER_PENDING
Bit
Position
Bit Field Name
Type
Reset
Description
7..1
RFU
R
0
Reserved
0
transfer_pending
R
0
The live status of the SPI Master. Set
to '1' when the SPI Master is busy
servicing a prior request.
Table 2.35 SPI Master Transfer Pending Register
The
transfer_pending
bit reports the status of the SPI Master in real time.
2.3.12
Use Cases
The SPI Master can be used in the following ways:
As a polled interface – writing a single byte at a time to the transmit register and reading single
byte responses from the receive register.
As an interrupt driven interface – an interrupt handler sends multiple bytes of data to the transmit
register and receives a corresponding amount of data from the receive register.
A DMA driven interface – two DMA engines are configured to send data to, and receive data from,
the SPI slave. Program code is not required to perform any actions during a transfer.
2.3.12.1
Interface Setup
To setup the SPI Master, go through the following steps:
1.
Reset the SPI Master in the
SPI_MASTER_CONTROL
register.
2.
Enable the SPI Master in the
SPI_MASTER_CONTROL
register.
3.
Set the required frequency of SCLK via the clock divisor in the
SPI_MASTER_CLK_DIV
register.
4.
Setup the SPI Master Mode and bit order as required in the
SPI_MASTER_SETUP
register.
5.
Leave the Slave Select line inactive.
6.
Set the desired Slave Select line and idle state in the
SPI_MASTER_SS_SETUP
register.
7.
The interface is now ready to use.
Enabling and Disabling Slave Select:
Manual control over SS# is performed by enabling or disabling SS# under program control via the
spi_ss_n
bit of the
SPI_MASTER_SETUP
register. The
SPI_MASTER_TRANSFER_SIZE_L
and
SPI_MASTER_TRANSFER_SIZE_U
registers must be zero for this method.
Alternatively, automatic control (where the amount of data to transfer is known in advance) is
done by leaving the Slave Select line inactive and programming the number of bytes to transfer
into the
SPI_MASTER_TRANSFER_SIZE
registers. SS# is enabled when data is next written to the
SPI_MASTER_TX_DATA
register and disabled automatically. To correctly enable SS# at the start of a
transfer program a non-zero value must be programmed into the
SPI_MASTER_DATA_DELAY
register.
Here is an example SPI Master setup that uses WRITE_IO_REG macro defined in 5.1.2.
WRITE_IO_REG(0x0050, 0x01); // Reset to a known state
WRITE_IO_REG(0x0050, 0x02); // Enable SPI Master device before any setup not after.
WRITE_IO_REG(0x0056, 0x60); // Divide the FT51A system clock by 0x60
WRITE_IO_REG(0x0058, 1 << 0x00 // Set SS Idle State to High,
| 0 << 0x01); // Set SS number to 0
WRITE_IO_REG(0x0055, 0 << 0x00 // Set SCLK phase to 0
| 0 << 0x01 // Set SCLK polarity to 0
| 0 << 0x02
// Set data order to MSB
