Application Note
AN_289 FT51A Programming Guide
Version 1.0
Document Reference No.: FT_000962 Clearance No.: FTDI# 483
124
Copyright © 2015 Future Technology Devices International Limited
The most appropriate unit to accurately represent the delay is the nanosecond. The type has to be
able to contain value 131070000 (MAX-MIN), which requires four bytes, as number 131070000 =
0x07CFF830. Therefore, the delay parameter in an example function should be of uint32_t type.
With the uint32_t type, the timer range becomes:
CLK [Hz]
Timer range
Timer 0 - 2
Timer A – D
48000000
84 ns - 16383750 ns
21 ns - 4294967295 ns (= 4.3 s)
(90 s if not limited by the
uint32_t type)
calculated by inverse of maximally
pre-scaled clock times max number of timer
increments = 1/(48MHz/65536))*65535
24000000
167 ns - 32767500 ns
42 ns - 4.3 s (179 s if not limited by the
uint32_t type)
12000000
334 ns - 65535000 ns
84 ns - 4.3 s (358 s if not
limited by the uint32_t type)
6000000
667 ns - 131070000 ns
167 ns - 4.3 s (720 s if not
limited by the uint32_t type)
Figure 2.10 Timer range for uint32_t timer
2.13.15.2
Watchdog
Software must feed the watchdog within a set period (as determined by the
timer_wdg_write
bit of
the
TIMER_WDG
register) to verify proper software execution. If a hardware or software failure
prevents feeding the watchdog within the minimum timeout period, the FT51A reset is forced.
Once the system has undergone the reset, it is possible to check with the
wdg_int
bit of the
TIMER_CONTROL_2
register whether the reset was caused by a watchdog overflow or normal reset.
The watchdog timer is disabled only by power-on reset and during power-down. Once enabled, it
cannot be disabled. It is enabled by the
start_wdg
bit of the
TIMER_CONTROL_
2 register.
Below are example functions that could be incorporated into user’s code.
/**
@brief Watchdog Enable
@details A function to start the watchdog.
@param[in] start_value Watchdog start value (only bits from 0 to 4 used).
@return void
**/
void
watchdog_enable
(uint8_t start_value)
{
// Initialise watchdog timer with the set Start Value.
WRITE_IO_REG(TIMER_WDG,
start_value & 0x1F);
// Watchdog interrupt enable.
WRITE_IO_REG(TIMER_CONTROL_2,
WDG_INT_IEN);
// Enable Timer.
WRITE_IO_REG(TIMER_CONTROL,
TIMER_DEV_EN);
// Clear the watchdog before the start is issued.
WRITE_IO_REG(TIMER_CONTROL_2,
