Mainboard User’s Manual
42
Chipset Features Setup
PCI Delay Transaction:
The chipset has an embedded 32-bit posted
write buffer to support delay transactions cycles. Enable to support
compliance with PCI specification version 2.1. The default is “En-
abled.”
PCI#2 Access #1 Retry:
When enabled, the AGP Bus (PCI#1) ac-
cess to PCI Bus (PCI#2) is executed with the error retry feature. The
default is “Enabled.”
AGP Master 1 WS Write:
This implements a single delay when
writing to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The default is “Disabled.”
AGP Master 1 WS Read:
This implements a single delay when
reading to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The default is “Disabled.”
Memory Parity/ECC Check:
Enable this item to allow BIOS to
perform a parity/ECC check to the POST memory tests. Enable only
if the system DRAM supports parity/ECC checking. Default is “Dis-
abled”.
CPU Vcore Select:
Enables you to set the CPU Vcore voltage. Op-
tions are:
•
Default (default)
•
+0.05V
•
+0.1V
•
+0.2V
•
+0.3V
•
+0.4V
•
-0.05V
•
-0.1V
After you have made your selections in the Chipset Features Setup
screen, press <ESC> to go back to the main screen.
Summary of Contents for P6F117
Page 1: ...P6F117 Mainboard Manual Friday March 02 2001 ...
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