Mainboard User’s Manual
40
Chipset Features Setup
Bank 0/1 2/3 4/5 DRAM Timing:
This item allows you to select the
value in the field, depending on whether the board has paged
DRAMs or EDO (extended data output) DRAMs. The following op-
tions are allowed:
•
FP/EDO 70ns
•
FP/EDO 70ns
•
Normal
•
Medium
•
Fast
•
Turbo
SDRAM Cycle Length:
This field enables you to set the CAS la-
tency time in HCLKs of 2/2 or 3/3. The system board designer
should have set the values in this field, depending on the DRAM in-
stalled. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
DRAM Clock:
Enables the user to select the DRA M Clock.
Memory Hole:
If Set to “Enabled”, when the system memory size is
equal to or greater than 16M bytes, the physical memory address
from 15M to 16M will be passed to PCI or ISA and there will be a 1
MB hole in your system memory. This option is designed for some
OS with special add-in cards which need 15-16 MB memory space.
The default setting is “Disabled.”
P2C/C2P Concurrency:
When disabled, the CPU bus is occupied
during the entire PCI operation period. The default is “Enabled.”
System BIOS Cacheable:
When set to “Enabled” (default), the Sys-
tem BIOS will be cached for faster execution.
Video RAM Cacheable:
When enabled, the graphics card’s local
memory will be cached for faster execution. However, if any pro-
gram writes to this memory area, a system error may result. The
default is “Enabled.”
AGP Aperture Size (MB):
This option determines the effective size
of the AGP Graphic
Aperture
, where memory-mapped graphic data
structures are located.
Summary of Contents for P6F117
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