background image

 QMAN: 333.333 MHz

 PME: 333.333 MHz

L1:      D-cache 32 kB enabled

 I-cache 32 kB enabled

Reset Configuration Word (RCW):

 00000000: 140c0019 0c101519 00000000 00400000

 00000010: 70701053 0044bc00 0c023000 0d000000

 00000020: 00000000 ee0000ee 00000000 000287fc

      00000030: 00000000 50000000 00000000 00000038

Board: T4240RDB, SERDES Reference Clocks: SERDES1=100MHz SERDES2=156.25MHz

SERDES3=100MHz SERDES4=100MHz

I2C: ready

SPI: ready

DRAM: Initializing....using SPD

Detected UDIMM 9JSF25672AZ-2G1K1

Detected UDIMM 9JSF25672AZ-2G1K1

Detected UDIMM 9JSF25672AZ-2G1K1

4 GiB left unmapped

     DDR: 6 GiB (DDR3, 64-bit, CL=11, ECC on)

 DDR Controller Interleaving Mode: 3-way 4KB

Flash: 128 MiB

L2: 2048 KB enabled

enable l2 for cluster 1 fec60000

enable l2 for cluster 2 feca0000

Corenet Platform Cache: 1536 KB enabled

Using SERDES1 Protocol: 28 (0x1c)

Using SERDES2 Protocol: 56 (0x38)

Using SERDES3 Protocol: 2 (0x2)

Using SERDES4 Protocol: 10 (0xa)

SRIO1: disabled

SRIO2: disabled

NAND: 2048 MiB

MMC: FSL_SDHC: 0

PCIe1: Root Complex, no link, regs @ 0xfe240000

PCIe1: Bus 00 - 00

PCIe3: Root Complex, no link, regs @ 0xfe260000

PCIe3: Bus 01 - 01

In: serial

Out: serial

Err: serial

Warning: SERDES2 expects reference clock 125MHz, but actual is 156.25MHz

Net: Fman1: Uploading microcode version 106.4.9

Fman2: Uploading microcode version 106.4.9

FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@TGEC1,

FM1@TGEC2, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4,

FM2@TGEC1, FM2@TGEC2

Hit any key to stop autoboot: 0

The system auto boots and shows the following Linux login screen.

Poky 9.0 (Yocto Project 1.4 Reference Distro) 1.4 t4240rdb ttyS0

t4240rdb login: root

root@t4240rdb:~# uname -a

Linux t4240rdb 3.8.13-rt9-g7a2b5bd-dirty #5 SMP Wed Jul 31 13:45:53 CST 2013

ppc64 GNU/Linux

root@t4240rdb:~#

4 SDK information

To access the SDK 

i

nformation on your Linux or Windows® based machine, follow these steps.

To mount an ISO image on a Linux based machine:

1. Locate the 

QorIQ-SDK-V1.4-SOURCE-20130830-yocto.iso

 image file in the SW image directory of the USB

memory stick.

SDK information

T4240RDB Quick Start Guide, Rev 0, 11/2013

Freescale Semiconductor, Inc.

3

Downloaded from

Arrow.com.

Downloaded from

Arrow.com.

Downloaded from

Arrow.com.

Summary of Contents for T4240RDB

Page 1: ... Rev 1 0 silicon and T4240RDB PB for a board based upon T4240 Rev 2 0 silicon After reading this document you will be familiar with Board configuration settings frequency boot location and T4240 or T4160 personality selection How to get started and boot uboot and Linux Freescale Semiconductor Document Number T4240RDBQS Quick Start Rev 0 11 2013 T4240RDB Quick Start Guide 2013 Freescale Semiconduct...

Page 2: ...ole tool on the host computer to communicate with the T4240RDB 6 Configure the host computer s serial port with the following settings Data rate 115200 bps Number of data bits 8 Parity None Number of stop bits 1 Flow control Hardware None 7 Switch on the power button on the front side of the chassis The board will boot and show the u boot console messages U Boot 2013 01 gecbda14 dirty Jul 31 2013 ...

Page 3: ...mplex no link regs 0xfe240000 PCIe1 Bus 00 00 PCIe3 Root Complex no link regs 0xfe260000 PCIe3 Bus 01 01 In serial Out serial Err serial Warning SERDES2 expects reference clock 125MHz but actual is 156 25MHz Net Fman1 Uploading microcode version 106 4 9 Fman2 Uploading microcode version 106 4 9 FM1 DTSEC1 PRIME FM1 DTSEC2 FM1 DTSEC3 FM1 DTSEC4 FM1 TGEC1 FM1 TGEC2 FM2 DTSEC1 FM2 DTSEC2 FM2 DTSEC3 F...

Page 4: ...umentation 7 Browse to the location where you extracted the ISO file and open STARTHERE html To mount an ISO image on a Windows based machine 1 Download and Install 7Zip 2 Locate the QorIQ SDK V1 4 SOURCE 20130830 yocto iso image file in the SW image directory of the USB memory stick 3 Copy the ISO file to your Documents folder or to your preferred location 4 Right click the ISO file and select Ex...

Page 5: ...emoving screws from top side of chassis 2 Remove both screws from the back side of the chassis as shown in the figure below Figure 4 Removing screws from back side of chassis 3 Remove the top cover carefully Removing the enclosure T4240RDB Quick Start Guide Rev 0 11 2013 Freescale Semiconductor Inc 5 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arro...

Page 6: ...RT2 USB1 USB2 Power button Reset Battery SW1 SW2 SW4 SW3 DIMM2 DIMM3 DIMM1 JP1 JTAG PCIex8 PCIex4 Figure 5 T4240RDB top view System board interface T4240RDB Quick Start Guide Rev 0 11 2013 6 Freescale Semiconductor Inc Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 7: ...erial Port RJ45 x2 I2C Bus 1 5 3 Gb s SATA II 480 Mbps USB 20 RS232 SerDes1 ABCD SerDes1 EFGH SerDes2 ABCD SerDes2 EFGH I2C UART USB 2 0 SerDes4 G IFC SDHC CH C CH B CH A DDR3 USB x 2 Figure 6 T4240RDB block diagram 6 2 Features Some key features of the T4240RDB are Freescale QorIQ Processing Platform QorIQ T4240 Communications Processor with 24 virtual cores 1 6 GHz Memory subsystem DDR3 SDRAM 3 ...

Page 8: ... and Ethernet LED are located at the front of the casing Power ATX Power Supply 300W 6 3 Port map The table below shows how ETH matches to Linux and Uboot Label on the Front Panel Label in Linux Label in Uboot ETH0 Fm1 mac1 FM1 DTSEC1 ETH1 Fm1 mac2 FM1 DTSEC2 ETH2 Fm1 mac3 FM1 DTSEC3 ETH3 Fm1 mac4 FM1 DTSEC4 ETH4 Fm2 mac1 FM2 DTSEC1 ETH5 Fm2 mac2 FM2 DTSEC2 ETH6 Fm2 mac3 FM2 DTSEC3 ETH7 Fm2 mac4 F...

Page 9: ...LK The table below shows the SW1 settings for SYSCLK DDRCLK ratio 4 1 Table 2 SW1 Settings 4 1 CPU Speed SYSCLK MHz DDRCLK MHz 0000 1667 66 67 66 67 0001 1667 66 67 100 0010 1667 66 67 125 0011 Default 1667 66 67 133 33 0100 1600 100 66 67 0101 1600 100 100 0110 1600 100 125 0111 1600 100 133 33 1000 X 125 66 67 Table continues on the next page Default boot mode T4240RDB Quick Start Guide Rev 0 11...

Page 10: ...icates off The default SW3 value is 1111 Table 3 SW3 Settings 3 1 Reserved RCW_BANK_SELECT 0 2 4 RCW_SRC_SELECT 0 RCW source from SD card 1 RCW source from EEPROM 8 4 SW4 switch The table below shows the SW4 settings where value 0 indicates on and value 1 indicates off Table 4 SW4 Settings P1 Auto power mode 0 Normal power on 1 Normal power on off default P2 CFG_TESTSEL_B 0 T4160 mode 1 T4240 mode...

Page 11: ...ble summarizes revisions to this document Table 6 Revision history Revision Date Description Rev 0 11 2013 Initial public release Jumper settings T4240RDB Quick Start Guide Rev 0 11 2013 Freescale Semiconductor Inc 11 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 12: ...s including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address freescale com SalesTermsandConditions Freescale the Freescale logo AltiVec CodeWarrior Energy...

Reviews: