Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual, Rev. 0
Freescale Semiconductor
14-1
Chapter 14
Shared Bus Arbiter
14.1
Introduction
14.1.1
Overview
The Shared Bus Arbiter provides coherent system bus arbitration between two Shared Bus masters
(Core-0/DMA0, Core-1/DMA1) using round-robin, fixed, and other methods. The Shared Bus Arbiter is
used when two masters access external memory, shared memory or shared peripherals, but only if both
masters are accessing the same endpoint. No arbitration occurs if each Shared Bus master accesses
different endpoints because there is no bus contention.
Figure 14-1. Shared Bus Arbiter
14.1.2
Features
Each Shared Bus is a multiplexed bus of the DSP core's P, X and Y buses and the DMA bus. Arbitration
on each Shared Bus between the DSP core and its DMA is configured by the Core-DMA Priority bits in
the OMR register (see
Chapter 5, “Core Configuration,”
for more information).
This section is limited to describing the arbitration between the shared bus for Core 0/DMA 0 and the
shared bus for Core 1/DMA 1.
The arbiter includes:
•
Flexible arbitration policy, which supports:
— Fixed arbitration method
— Round-robin arbitration method
— Specific arbitration for continuous transfer
•
Arbitration happens only when the current access is enabled and
in active address scope
•
Zero-cycle delay in arbitration
Shared Bus Master 0
(Core-0/DMA0)
Shared Bus Master 1
(Core-1/DMA1)
Shared Bus
Arbiter
Shared Bus
Slave
Arbitration Method Control